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    Integrated analog video receiver
    1.
    发明授权
    Integrated analog video receiver 失效
    集成模拟视频接收器

    公开(公告)号：US08203653B2

    公开(公告)日：2012-06-19

    申请号：US12191905

    申请日：2008-08-14

    Applicant: Weijie Yun ,  Samuel Sheng ,  Dennis G. Yee

    Inventor： Weijie Yun ,  Samuel Sheng ,  Dennis G. Yee

    IPC: H04N5/44

    CPC classification number: H03D3/008 ,  H03D7/165 ,  H03D2200/0047 ,  H04L25/061 ,  H04L27/063 ,  H04N5/44 ,  H04N5/455 ,  H04N5/50 ,  H04N5/63

    Abstract: An analog video receiver implemented in an integrated circuit device. The analog video receiver includes an amplifier to amplify an analog video signal having a desired carrier frequency, and a mixing circuit to mix the amplified analog video signal with a complex sinusoid having a frequency substantially equal to the carrier frequency.

    Abstract translation: 在集成电路器件中实现的模拟视频接收器。 模拟视频接收机包括用于放大具有期望载波频率的模拟视频信号的放大器，以及混合电路，用于将放大的模拟视频信号与具有基本上等于载波频率的频率的复数正弦曲线混合。

    Video receiver with DC offset cancellation
    2.
    发明授权
    Video receiver with DC offset cancellation 有权
    具有DC偏移消除的视频接收器

    公开(公告)号：US08077262B2

    公开(公告)日：2011-12-13

    申请号：US12043370

    申请日：2008-03-06

    Applicant: Weijie Yun ,  Samuel Sheng

    Inventor： Weijie Yun ,  Samuel Sheng

    IPC: H04N5/44

    CPC classification number: H03D3/008 ,  H03D7/165 ,  H03D2200/0047 ,  H04L25/061 ,  H04L27/063 ,  H04N5/44 ,  H04N5/455 ,  H04N5/50 ,  H04N5/63

    Abstract: An analog video receiver implemented in an integrated circuit device. The analog video receiver includes a mixing circuit to mix an analog video signal with a sinusoid to generate a frequency-shifted analog video signal, and an offset cancellation circuit to obtain a sample of the frequency-shifted analog video signal during a first time interval and, based on the sample, generate an offset cancellation signal that, when summed with the frequency-shifted analog video signal, reduces a substantially time-invariant offset in the frequency-shifted analog video signal.

    Abstract translation: 在集成电路器件中实现的模拟视频接收器。 模拟视频接收机包括：混合电路，用于将模拟视频信号与正弦曲线混合以产生频移模拟视频信号;以及偏移消除电路，以在第一时间间隔内获得频移模拟视频信号的采样;以及 基于该采样产生偏移抵消信号，该偏移抵消信号当与频移模拟视频信号相加时，减少频移模拟视频信号中的基本上时间不变的偏移。

    Video receiver with DC offset cancellation
    3.
    发明申请
    Video receiver with DC offset cancellation 有权
    具有DC偏移消除的视频接收器

    公开(公告)号：US20050243217A1

    公开(公告)日：2005-11-03

    申请号：US11120378

    申请日：2005-05-02

    Applicant: Weijie Yun ,  Samuel Sheng

    Inventor： Weijie Yun ,  Samuel Sheng

    IPC: H03D3/00 ,  H03D7/16 ,  H04L25/06 ,  H04L27/06 ,  H04N5/44 ,  H04N5/455 ,  H04N5/50 ,  H04N5/63

    CPC classification number: H03D3/008 ,  H03D7/165 ,  H03D2200/0047 ,  H04L25/061 ,  H04L27/063 ,  H04N5/44 ,  H04N5/455 ,  H04N5/50 ,  H04N5/63

    Abstract: An analog video receiver implemented in an integrated circuit device. The analog video receiver includes a mixing circuit to mix an analog video signal with a sinusoid to generate a frequency-shifted analog video signal, and an offset cancellation circuit to obtain a sample of the frequency-shifted analog video signal during a first time interval and, based on the sample, generate an offset cancellation signal that, when summed with the frequency-shifted analog video signal, reduces a substantially time-invariant offset in the frequency-shifted analog video signal.

    Abstract translation: 在集成电路器件中实现的模拟视频接收器。 模拟视频接收机包括：混合电路，用于将模拟视频信号与正弦曲线混合以产生频移模拟视频信号;以及偏移消除电路，以在第一时间间隔内获得频移模拟视频信号的采样;以及 基于该采样产生偏移抵消信号，该偏移抵消信号当与频移模拟视频信号相加时，减少频移模拟视频信号中的基本上时间不变的偏移。

    Integrated analog video receiver
    4.
    发明授权
    Integrated analog video receiver 失效
    集成模拟视频接收器

    公开(公告)号：US07932958B2

    公开(公告)日：2011-04-26

    申请号：US12403348

    申请日：2009-03-12

    Applicant: Weijie Yun ,  Samuel Sheng ,  Dennis G. Yee

    Inventor： Weijie Yun ,  Samuel Sheng ,  Dennis G. Yee

    IPC: H04N5/44

    CPC classification number: H03D3/008 ,  H03D7/165 ,  H03D2200/0047 ,  H04L25/061 ,  H04L27/063 ,  H04N5/44 ,  H04N5/455 ,  H04N5/50 ,  H04N5/63

    Abstract: An analog video receiver implemented in an integrated circuit device. The analog video receiver includes an amplifier to amplify an analog video signal having a desired carrier frequency, and a mixing circuit to mix the amplified analog video signal with a complex sinusoid having a frequency substantially equal to the carrier frequency.

    Abstract translation: 在集成电路器件中实现的模拟视频接收器。 模拟视频接收机包括用于放大具有期望载波频率的模拟视频信号的放大器，以及混合电路，用于将放大的模拟视频信号与具有基本上等于载波频率的频率的复数正弦曲线混合。

    Phase-noise mitigation in an integrated analog video receiver
    6.
    发明申请
    Phase-noise mitigation in an integrated analog video receiver 失效

    公开(公告)号：US20060017856A1

    公开(公告)日：2006-01-26

    申请号：US11232579

    申请日：2005-09-21

    Applicant: Samuel Sheng ,  Weijie Yun

    Inventor： Samuel Sheng ,  Weijie Yun

    IPC: H04N5/44

    CPC classification number: H04N9/646

    Abstract: Phase noise mitigation in an analog video receiver implemented in an integrated circuit device. A phase correction value that indicates a phase offset between a synthesized sinusoid and a reference sinusoid conveyed in a horizontal retrace region of a composite video signal is periodically generated. A phase error that will accumulate during an interval between horizontal retrace regions of the composite video signal is estimated based, at least in part, on the phase correction value, and the phase of a chroma signal component of the composite video signal is adjusted based on the estimated phase error.

    Video receiver with reduced power mode
    7.
    发明授权
    Video receiver with reduced power mode 有权
    具有降低功耗模式的视频接收器

    公开(公告)号：US07929060B2

    公开(公告)日：2011-04-19

    申请号：US11120377

    申请日：2005-05-02

    Applicant: Weijie Yun ,  Samuel Sheng

    Inventor： Weijie Yun ,  Samuel Sheng

    IPC: H04N5/63

    CPC classification number: H03D3/008 ,  H03D7/165 ,  H03D2200/0047 ,  H04L25/061 ,  H04L27/063 ,  H04N5/44 ,  H04N5/455 ,  H04N5/50 ,  H04N5/63

    Abstract: An integrated circuit device having a television signal tuner, video decoder and power control circuit. The television signal tuner selects one of a plurality of television channels, and the video decoder converts a television signal conveyed in the selected television channel into a video display signal. The power control circuit alternately enables and disables the television tuner to enable reception of a first portion of video information conveyed in the television signal and to disable reception of a second portion of the video information.

    Abstract translation: 一种具有电视信号调谐器，视频解码器和功率控制电路的集成电路装置。 电视信号调谐器选择多个电视频道中的一个，并且视频解码器将在所选择的电视频道中传送的电视信号转换为视频显示信号。 功率控制电路交替地启用和禁用电视调谐器以能够接收在电视信号中传送的视频信息的第一部分，并且禁止接收视频信息的第二部分。

    PILOT-TONE CALIBRATION FOR TIME-INTERLEAVED ANALOG-TO-DIGITAL CONVERTERS
    8.
    发明申请
    PILOT-TONE CALIBRATION FOR TIME-INTERLEAVED ANALOG-TO-DIGITAL CONVERTERS 有权
    用于时间间隔的模拟数字转换器的导频校准

    公开(公告)号：US20080030387A1

    公开(公告)日：2008-02-07

    申请号：US11871953

    申请日：2007-10-12

    Applicant: Samuel Sheng ,  Weijie Yun

    Inventor： Samuel Sheng ,  Weijie Yun

    IPC: H03M1/10

    CPC classification number: H03M1/1014 ,  H03M1/1215 ,  H04N5/44 ,  H04N5/4401 ,  H04N5/4446 ,  H04N5/455 ,  H04N21/4263

    Abstract: A self-calibrating analog-to-digital converter (ADC). The ADC includes multiple component ADCs to generate respective digital representations of an input signal in response to respective timing signals that are offset in phase from one another, each component ADC having a gain setting that controls a magnitude of the digital representations. The ADC further includes correction circuitry to generate a plurality of fast-Fourier transforms (FFTs) that correspond to the digital representations of the input signal and to adjust the gain settings of the component ADCs and/or phase angles of the timing signals based on gain and phase errors indicated by the FFTs.

    Abstract translation: 自校准模数转换器（ADC）。 ADC包括多个分量ADC，以响应于彼此相位偏移的相应定时信号来产生输入信号的相应数字表示，每个分量ADC具有控制数字表示幅度的增益设置。 ADC还包括校正电路，用于产生对应于输入信号的数字表示的多个快速傅里叶变换（FFT），并且基于增益来调整分量ADC的增益设置和/或定时信号的相位角 和由FFT表示的相位误差。

    Pilot-tone calibration for time-interleaved analog-to-digital converters
    9.
    发明授权
    Pilot-tone calibration for time-interleaved analog-to-digital converters 有权
    用于时间交织的模数转换器的导频校准

    公开(公告)号：US07283074B2

    公开(公告)日：2007-10-16

    申请号：US11232580

    申请日：2005-09-21

    Applicant: Samuel Sheng ,  Weijie Yun

    Inventor： Samuel Sheng ,  Weijie Yun

    IPC: H03M1/10

    CPC classification number: H03M1/1014 ,  H03M1/1215 ,  H04N5/44 ,  H04N5/4401 ,  H04N5/4446 ,  H04N5/455 ,  H04N21/4263

    Abstract: A self-calibrating analog-to-digital converter (ADC). The ADC includes multiple component ADCs to generate respective digital representations of an input signal in response to respective timing signals that are offset in phase from one another, each component ADC having a gain setting that controls a magnitude of the digital representations. The ADC further includes correction circuitry to generate a plurality of fast-Fourier transforms (FFTs) that correspond to the digital representations of the input signal and to adjust the gain settings of the component ADCs and/or phase angles of the timing signals based on gain and phase errors indicated by the FFTs.

    Abstract translation: 自校准模数转换器（ADC）。 ADC包括多个分量ADC，以响应于彼此相位偏移的相应定时信号来产生输入信号的相应数字表示，每个分量ADC具有控制数字表示的幅度的增益设置。 ADC还包括校正电路，用于产生对应于输入信号的数字表示的多个快速傅里叶变换（FFT），并且基于增益来调整分量ADC的增益设置和/或定时信号的相位角 和由FFT表示的相位误差。

    Pilot-tone calibration for time-interleaved analog-to-digital converters
    10.
    发明授权
    Pilot-tone calibration for time-interleaved analog-to-digital converters 有权
    用于时间交织的模数转换器的导频校准

    公开(公告)号：US07675441B2

    公开(公告)日：2010-03-09

    申请号：US11871953

    申请日：2007-10-12

    Applicant: Samuel Sheng ,  Weijie Yun

    Inventor： Samuel Sheng ,  Weijie Yun

    IPC: H03M1/10

    CPC classification number: H03M1/1014 ,  H03M1/1215 ,  H04N5/44 ,  H04N5/4401 ,  H04N5/4446 ,  H04N5/455 ,  H04N21/4263

    Abstract: A self-calibrating analog-to-digital converter (ADC). The ADC includes multiple component ADCs to generate respective digital representations of an input signal in response to respective timing signals that are offset in phase from one another, each component ADC having a gain setting that controls a magnitude of the digital representations. The ADC further includes correction circuitry to generate a plurality of fast-Fourier transforms (FFTs) that correspond to the digital representations of the input signal and to adjust the gain settings of the component ADCs and/or phase angles of the timing signals based on gain and phase errors indicated by the FFTs.

    Abstract translation: 自校准模数转换器（ADC）。 ADC包括多个分量ADC，以响应于彼此相位偏移的相应定时信号来产生输入信号的相应数字表示，每个分量ADC具有控制数字表示幅度的增益设置。 ADC还包括校正电路，用于产生对应于输入信号的数字表示的多个快速傅里叶变换（FFT），并且基于增益来调整分量ADC的增益设置和/或定时信号的相位角 和由FFT表示的相位误差。

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