公开(公告)号：US07884875B2

公开(公告)日：2011-02-08

申请号：US11866940

申请日：2007-10-03

申请人： Yong-Chai Kwon ,  Dong-Ho Lee

发明人： Yong-Chai Kwon ,  Dong-Ho Lee

IPC分类号： H04N5/225 ,  H01L21/00

CPC分类号： H01L27/14618 ,  H01L24/97 ,  H01L27/14625 ,  H01L27/14685 ,  H01L31/0203 ,  H01L31/0232 ,  H01L2224/48091 ,  H01L2224/48235 ,  H01L2924/12043 ,  H04N5/2257 ,  H01L2924/00014 ,  H01L2924/00

摘要： Provided are a camera module and a method of fabricating the same. The method includes preparing a lens structure including upper connection portions. Lower connection portions are formed in a predetermined region of a substrate. The lower connection portions define a chip region and fit in the upper connection portions, respectively. An image sensor chip is located on the bottom surface of the chip region. The lens structure is adhered to the substrate using the upper and lower connection portions.

摘要翻译： 提供了一种相机模块及其制造方法。 该方法包括制备包括上连接部分的透镜结构。 下连接部分形成在基板的预定区域中。 下连接部分分别限定芯片区域并配合在上连接部分中。 图像传感器芯片位于芯片区域的底表面上。 透镜结构使用上连接部分和下连接部分粘合到基板上。

公开(公告)号：US07777323B2

公开(公告)日：2010-08-17

申请号：US11750663

申请日：2007-05-18

申请人： Yong Chai Kwon ,  Keum-Hee Ma ,  Kang-Wook Lee ,  Dong-Ho Lee ,  Seong-il Han

发明人： Yong Chai Kwon ,  Keum-Hee Ma ,  Kang-Wook Lee ,  Dong-Ho Lee ,  Seong-il Han

IPC分类号： H01L23/12 ,  H01L21/44

CPC分类号： H01L21/76898 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/05009 ,  H01L2224/06181 ,  H01L2224/13009 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16147 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2924/01327 ,  H01L2924/15311 ,  H01L2924/00

摘要： Example embodiments are directed to a method of forming a semiconductor structure and a semiconductor structure including a semiconductor unit including a protrusion on a front side of the semiconductor unit and a recess on a backside of the semiconductor unit.

摘要翻译： 示例性实施例涉及一种形成半导体结构的方法和包括半导体单元的半导体结构的方法，所述半导体单元包括在半导体单元的前侧上的突起和半导体单元的背侧上的凹部。

公开(公告)号：US20070007641A1

公开(公告)日：2007-01-11

申请号：US11348670

申请日：2006-02-06

申请人： Kang-Wook Lee ,  Gu-Sung Kim ,  Yong-Chai Kwon ,  Keum-Hee Ma ,  Seong-Il Han

发明人： Kang-Wook Lee ,  Gu-Sung Kim ,  Yong-Chai Kwon ,  Keum-Hee Ma ,  Seong-Il Han

IPC分类号： H01L23/52

CPC分类号： H01L25/0657 ,  H01L23/5389 ,  H01L24/24 ,  H01L24/82 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/16 ,  H01L2224/24226 ,  H01L2224/24227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/83192 ,  H01L2224/97 ,  H01L2225/0652 ,  H01L2225/06541 ,  H01L2225/06551 ,  H01L2225/06572 ,  H01L2225/06586 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01076 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/157 ,  H01L2924/181 ,  H01L2924/30105 ,  H01L2924/00 ,  H01L2224/83 ,  H01L2224/82 ,  H01L2924/00012

摘要： A method for fabricating a chip-embedded interposer may comprise forming at least one cavity on a silicon substrate, forming a plurality of through vias penetrating the silicon substrate, providing an integrated circuit chip having a plurality of I/O pads, and forming rerouting conductors connected to the I/O pads and the through vias. A stack structure having different kinds of chips may be incorporated at wafer level using the described interposer.

摘要翻译： 芯片嵌入式插入器的制造方法可以包括在硅衬底上形成至少一个空腔，形成穿过硅衬底的多个通孔，提供具有多个I / O焊盘的集成电路芯片，以及形成重新布线的导体 连接到I / O焊盘和通孔。 具有不同种类的芯片的堆叠结构可以使用所描述的插入器结合在晶片级。

公开(公告)号：US20100207278A1

公开(公告)日：2010-08-19

申请号：US12769232

申请日：2010-04-28

申请人： Yong-Chai Kwon ,  Dong-Ho Lee

发明人： Yong-Chai Kwon ,  Dong-Ho Lee

IPC分类号： H01L23/52

CPC分类号： H01L25/0657 ,  H01L23/481 ,  H01L23/5258 ,  H01L25/50 ,  H01L2224/02371 ,  H01L2224/02372 ,  H01L2224/04105 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05569 ,  H01L2224/13008 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2924/00014 ,  H01L2224/05599 ,  H01L2224/05099

摘要： A semiconductor package structure is disclosed. The semiconductor package structure includes semiconductor chips on a semiconductor substrate. Each of the semiconductor chips includes chip pads. Through-vias extend through each of the semiconductor chips. Redistribution structures and a chip selection interconnection line are disposed on each of the semiconductor chips. The redistribution structures electrically connect at least one of the through-vias with at least one of the chip pads. Each chip selection interconnection line includes first regions connected to a corresponding number of the through-vias and a second region connecting at least one of the first regions with one of the chip pads. The semiconductor chips are stacked and electrically connected using the through-vias.

摘要翻译： 公开了半导体封装结构。 半导体封装结构包括半导体衬底上的半导体芯片。 每个半导体芯片包括芯片焊盘。 贯通孔延伸穿过每个半导体芯片。 再分配结构和芯片选择互连线设置在每个半导体芯片上。 再分配结构将至少一个通孔与至少一个芯片焊盘电连接。 每个芯片选择互连线包括连接到对应数量的通孔的第一区域和将至少一个第一区域与其中一个芯片焊盘连接的第二区域。 半导体芯片使用贯通孔堆叠并电连接。

公开(公告)号：US20090186446A1

公开(公告)日：2009-07-23

申请号：US12313980

申请日：2008-11-26

申请人： Yong-Chai Kwon ,  Nam-Seog Kim ,  Keum-Hee Ma ,  Ho-Jin Lee

发明人： Yong-Chai Kwon ,  Nam-Seog Kim ,  Keum-Hee Ma ,  Ho-Jin Lee

IPC分类号： H01L21/50

CPC分类号： H01L23/3128 ,  H01L23/055 ,  H01L23/10 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/97 ,  H01L2225/06572 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2224/81 ,  H01L2924/00

摘要： Provided are semiconductor device packages and methods for fabricating the same. In some embodiments, the method includes providing a semiconductor chip on a substrate with through electrodes formed in the substrate, and providing a capping layer on the substrate to receive the semiconductor chip in a recess formed in the capping layer. The capping layer is coupled to the substrate by a bonding layer formed on the substrate, and the capping layer covers the semiconductor chip provided on the substrate. The processing of the substrate and the capping layer can be separately performed, thus allowing the material for the capping layer and/or the substrate to be selected to reduce (e.g., to minimize) a difference between the thermal expansion coefficients of the capping layer material and the substrate material.

摘要翻译： 提供半导体器件封装及其制造方法。 在一些实施例中，该方法包括在基板上提供半导体芯片，该基板上形成有贯通电极，并在基板上提供覆盖层，以将半导体芯片接收在形成于封盖层中的凹槽中。 覆盖层通过形成在基板上的接合层耦合到基板，并且覆盖层覆盖设置在基板上的半导体芯片。 衬底和封盖层的处理可以分别进行，从而允许选择覆盖层和/或衬底的材料以减小（例如，最小化）封盖层材料的热膨胀系数之间的差异 和基材。

公开(公告)号：US20090121323A1

公开(公告)日：2009-05-14

申请号：US12266748

申请日：2008-11-07

申请人： Yong-Chai KWON ,  Nam-Seong KIM

发明人： Yong-Chai KWON ,  Nam-Seong KIM

IPC分类号： H01L23/48

CPC分类号： H01L21/76898 ,  H01L23/481 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/16 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/15311

摘要： A semiconductor device and a method of fabricating the same. The semiconductor device includes a semiconductor substrate including an active surface and an inactive surface which faces the active surface, a device isolation layer and a pad stacked on the active surface; and a through electrode disposed in a first via hole and a second via hole and including a protruding part that protrudes from the pad, the first via hole penetrating the semiconductor substrate, the second via hole penetrating the device insulation layer and the pad continuously, wherein at least a surface of the protruding part of the through electrode is formed of an oxidation resistance-conductive material.

摘要翻译： 一种半导体器件及其制造方法。 半导体器件包括：半导体衬底，其包括活性表面和面向有源表面的无活性表面;器件隔离层和堆叠在有源表面上的焊盘; 以及设置在第一通孔中的贯通电极和第二通孔，并且包括从所述焊盘突出的突出部分，所述第一通孔贯穿所述半导体基板，所述第二通孔贯穿所述器件绝缘层和所述焊盘，其中， 贯通电极的突出部分的至少一个表面由抗氧化传导材料形成。

公开(公告)号：US20080087974A1

公开(公告)日：2008-04-17

申请号：US11866940

申请日：2007-10-03

申请人： Yong-Chai KWON ,  Dong-Ho LEE

发明人： Yong-Chai KWON ,  Dong-Ho LEE

IPC分类号： H01L31/0232 ,  H01L31/18

CPC分类号： H01L27/14618 ,  H01L24/97 ,  H01L27/14625 ,  H01L27/14685 ,  H01L31/0203 ,  H01L31/0232 ,  H01L2224/48091 ,  H01L2224/48235 ,  H01L2924/12043 ,  H04N5/2257 ,  H01L2924/00014 ,  H01L2924/00

摘要： Provided are a camera module and a method of fabricating the same. The method includes preparing a lens structure including upper connection portions. Lower connection portions are formed in a predetermined region of a substrate. The lower connection portions define a chip region and fit in the upper connection portions, respectively. An image sensor chip is located on the bottom surface of the chip region. The lens structure is adhered to the substrate using the upper and lower connection portions.

摘要翻译： 提供了一种相机模块及其制造方法。 该方法包括制备包括上连接部分的透镜结构。 下连接部分形成在基板的预定区域中。 下连接部分分别限定芯片区域并配合在上连接部分中。 图像传感器芯片位于芯片区域的底表面上。 透镜结构使用上连接部分和下连接部分粘合到基板上。

公开(公告)号：US20070264745A1

公开(公告)日：2007-11-15

申请号：US11878220

申请日：2007-07-23

申请人： Yong-Chai Kwon ,  Kang-Wook Lee ,  Gu-Sung Kim ,  Seong-Il Han ,  Keum-Hee Ma ,  Suk-Chae Kang ,  Dong-Hyeon Jang

发明人： Yong-Chai Kwon ,  Kang-Wook Lee ,  Gu-Sung Kim ,  Seong-Il Han ,  Keum-Hee Ma ,  Suk-Chae Kang ,  Dong-Hyeon Jang

IPC分类号： H01L31/18

CPC分类号： H01L27/14618 ,  H01L27/1464 ,  H01L27/14685 ,  H01L2224/48091 ,  H04N5/2257 ,  H01L2924/00014

摘要： An image sensor device including a protective plate may be manufactured from an image sensor chip having an active surface and a back surface opposite to the active surface. The image sensor chip may include chip pads formed in a peripheral region of the active surface, a microlens formed in a central region of the active surface and an intermediate region between the peripheral and central regions. A protective plate may be attached to the intermediate region of the active surface of the image sensor chip using an adhesive pattern that is sized and configured to maintain a separation distance between the protective plate and the microlens formed on the image sensor chip. Conductive plugs, formed before, during or after the manufacture of the image sensor chip circuitry may provide electrical connection between the chip pads and external connectors.

摘要翻译： 包括保护板的图像传感器装置可以由具有与活性表面相对的活性表面和背面的图像传感器芯片制造。 图像传感器芯片可以包括形成在有源表面的周边区域中的芯片焊盘，形成在有源表面的中心区域中的微透镜和在周边区域和中心区域之间的中间区域。 可以使用粘合剂图案将保护板附接到图像传感器芯片的有效表面的中间区域，该粘合剂图案的尺寸和构造用于保持保护板和形成在图像传感器芯片上的微透镜之间的间隔距离。 在图像传感器芯片电路制造之前，期间或之后形成的导电插塞可以提供芯片焊盘和外部连接器之间的电连接。

公开(公告)号：US20070048969A1

公开(公告)日：2007-03-01

申请号：US11436851

申请日：2006-05-18

申请人： Yong-Chai Kwon ,  Kang-Wook Lee ,  Keum-Hee Ma ,  Seong-II Han

发明人： Yong-Chai Kwon ,  Kang-Wook Lee ,  Keum-Hee Ma ,  Seong-II Han

IPC分类号： H01L21/30

CPC分类号： H01L25/0657 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/11 ,  H01L24/12 ,  H01L24/16 ,  H01L24/31 ,  H01L24/83 ,  H01L24/90 ,  H01L24/94 ,  H01L25/50 ,  H01L2221/68372 ,  H01L2224/02311 ,  H01L2224/02321 ,  H01L2224/0401 ,  H01L2224/05568 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/08112 ,  H01L2224/13009 ,  H01L2224/13021 ,  H01L2224/13099 ,  H01L2224/16145 ,  H01L2224/16147 ,  H01L2224/16237 ,  H01L2224/2919 ,  H01L2224/81141 ,  H01L2224/83136 ,  H01L2224/83194 ,  H01L2224/838 ,  H01L2225/06513 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/0665 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2224/05552

摘要： In a stacked chip configuration, and manufacturing methods thereof, the gap between a lower and an upper chip is filled completely using a relatively simple process that eliminates voids between the lower and upper chips and the cracking and delamination problems associated with such voids. The present invention is applicable to both chip-level bonding and wafer-level bonding approaches. A photosensitive polymer layer is applied to a first chip, or wafer, prior to stacking the chips or stacking the wafers. The photosensitive polymer layer is partially cured, so that the photosensitive polymer layer is made to be structurally stable, while retaining its adhesive properties. The second chip, or wafer, is stacked, aligned, and bonded to the first chip, or wafer, and the photosensitive polymer layer is then cured to fully bond the first and second chips, or wafers. In this manner, adhesion between chips/wafers is greatly improved, while providing complete gap fill. In addition, mechanical reliability is improved, alleviating the problems associated with cracking and delamination, and leading to an improvement in device yield and device reliability.

摘要翻译： 在堆叠式芯片构造及其制造方法中，使用消除下部和上部切屑之间的空隙以及与这种空隙相关的裂纹和分层问题的相对简单的工艺，完全填充下部和上部切屑之间的间隙。 本发明可应用于芯片级接合和晶片级接合方式。 在堆叠芯片或堆叠晶片之前，将光敏聚合物层施加到第一芯片或晶片。 感光性聚合物层被部分固化，使得光敏聚合物层在结构上稳定，同时保持其粘合性能。 第二芯片或晶片被堆叠，对准并且结合到第一芯片或晶片，然后使光敏聚合物层固化以完全结合第一和​​第二芯片或晶片。 以这种方式，在提供完全的间隙填充的同时，大大提高了芯片/晶片之间的粘附。 此外，机械可靠性得到改善，减轻了与开裂和分层相关的问题，从而提高了设备​​的产量和设备的可靠性。

公开(公告)号：US20070045836A1

公开(公告)日：2007-03-01

申请号：US11436822

申请日：2006-05-18

申请人： Yong-Chai Kwon ,  Kang-Wook Lee ,  Keum-Hee Ma ,  Seong-Il Han ,  Dong-Ho Lee

发明人： Yong-Chai Kwon ,  Kang-Wook Lee ,  Keum-Hee Ma ,  Seong-Il Han ,  Dong-Ho Lee

IPC分类号： H01L23/48

CPC分类号： H01L25/0657 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/11 ,  H01L24/12 ,  H01L24/16 ,  H01L24/31 ,  H01L24/83 ,  H01L24/90 ,  H01L24/94 ,  H01L25/50 ,  H01L2221/68372 ,  H01L2224/02311 ,  H01L2224/02321 ,  H01L2224/0401 ,  H01L2224/05568 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/08112 ,  H01L2224/13009 ,  H01L2224/13021 ,  H01L2224/13099 ,  H01L2224/16145 ,  H01L2224/16147 ,  H01L2224/16237 ,  H01L2224/2919 ,  H01L2224/81141 ,  H01L2224/83136 ,  H01L2224/83194 ,  H01L2224/838 ,  H01L2225/06513 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/0665 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2224/05552

摘要： In a stacked chip configuration, and manufacturing methods thereof, the gap between a lower chip and an upper chip is filled completely using a relatively simple process that eliminates voids between the lower and upper chips and the cracking and delamination problems associated with voids. The present invention is applicable to both chip-level bonding and wafer-level bonding approaches. A photosensitive polymer layer is applied to a first chip, or wafer, prior to stacking the chips or stacking the wafers. The photosensitive polymer layer is partially cured, so that the photosensitive polymer layer is made to be structurally stable, while retaining its adhesive properties. The second chip, or wafer, is stacked, aligned, and bonded to the first chip, or wafer, and the photosensitive polymer layer is then cured to fully bond the first and second chips, or wafers. In this manner, adhesion between chips/wafers is greatly improved, while providing complete fill of the gap. In addition, mechanical reliability is improved and CTE mismatch is reduced, alleviating the problems associated with warping, cracking and delamination, and leading to an improvement in device yield and device reliability.

摘要翻译： 在堆叠式芯片结构及其制造方法中，使用消除下部和上部芯片之间的空隙以及与空隙相关的开裂和分层问题的相对简单的工艺，完全填充下部芯片和上部芯片之间的间隙。 本发明可应用于芯片级接合和晶片级接合方式。 在堆叠芯片或堆叠晶片之前，将光敏聚合物层施加到第一芯片或晶片。 感光性聚合物层被部分固化，使得光敏聚合物层在结构上稳定，同时保持其粘合性能。 第二芯片或晶片被堆叠，对准并且结合到第一芯片或晶片，然后使光敏聚合物层固化以完全结合第一和​​第二芯片或晶片。 以这种方式，在提供间隙的完全填充的同时，大大提高了芯片/晶片之间的粘附。 另外，提高了机械可靠性，降低了CTE失配，缓解了翘曲，开裂，脱层等问题，提高了设备​​的产量和设备的可靠性。