公开(公告)号：US07408733B2

公开(公告)日：2008-08-05

申请号：US11400579

申请日：2006-04-07

Applicant: Naoki Satoh ,  Yoshiteru Ishida ,  Yoshiju Watanabe ,  Terumi Takashi

Inventor： Naoki Satoh ,  Yoshiteru Ishida ,  Yoshiju Watanabe ,  Terumi Takashi

IPC: G11B5/596 ,  G11B19/26

CPC classification number: G11B19/26

Abstract: Embodiments of the invention increase the convenience of a magnetic disk drive for portable use by shortening a period of time required to record a large amount of data, and by increasing the reproduction time, in the magnetic disk drive. In one embodiment, an area between servo data parts is interpolated by servo data parts, each of which stores a burst signal, so that the allocation density of a burst signal is made k times. At the time of write operation in which data is written, only the servo data parts are made use of to perform the servo control while a disk is driven at high rotational speed so as to reduce the recording time. At the time of read operation in which data is reproduced, the servo data parts are made use of to ensure the required precision of the servo control at low rotational speed that is 1/k of the rotational speed at the time of write operation. The reproduction at low rotational speed enables the reduction in power consumption.

Abstract translation: 本发明的实施例通过缩短记录大量数据所需的时间周期以及通过增加磁盘驱动器中的再现时间来增加用于便携式使用的磁盘驱动器的便利性。 在一个实施例中，伺服数据部分之间的区域由伺服数据部分内插，每个伺服数据部分存储脉冲串信号，使得脉冲信号的分配密度为k次。 在写入数据的写入操作时，仅利用伺服数据部分来执行伺服控制，同时以高转速驱动盘，以便减少记录时间。 在再现数据的读取操作时，利用伺服数据部分来确保在写入操作时转速为1 / k的低转速下的伺服控制所要求的精度。 在低转速下的再现能够降低功耗。

公开(公告)号：US20080025178A1

公开(公告)日：2008-01-31

申请号：US11881188

申请日：2007-07-25

Applicant: Yasuhiro Takase ,  Yoshiteru Ishida

Inventor： Yasuhiro Takase ,  Yoshiteru Ishida

IPC: G11B5/58

CPC classification number: G11B20/1833 ,  G11B2220/2516 ,  H03M13/03 ,  H03M13/09 ,  H03M13/096 ,  H03M13/13 ,  H03M13/2906 ,  H03M13/3776

Abstract: Embodiments of the present invention provide a data recording apparatus, recording medium and error detection method capable of detecting an error while a ratio of an error detecting code to a data string recorded in the recording medium is restrained. According to one embodiment, since a recording composite code CX smaller in size than the case where error detecting codes generated from data sectors are connected to the data sectors (small sectors) D0 to D7 is added to data string, enough capacity is ensured to record the user data on a magnetic disk.

Abstract translation: 本发明的实施例提供一种能够检测错误的数据记录装置，记录介质和错误检测方法，同时抑制了记录在记录介质中的数据串的错误检测码的比率。 根据一个实施例，由于与数据扇区（小扇区）D 0至D 7连接的从数据扇区产生的错误检测码连接的尺寸小的记录复合码CX被添加到数据串，所以确保足够的容量 将用户数据记录在磁盘上。

公开(公告)号：US5636254A

公开(公告)日：1997-06-03

申请号：US430534

申请日：1995-04-25

Applicant: Kenichi Hase ,  Ryutaro Horita ,  Kunio Watanabe ,  Yoshiteru Ishida ,  Takashi Nara ,  Hiroshi Kimura

Inventor： Kenichi Hase ,  Ryutaro Horita ,  Kunio Watanabe ,  Yoshiteru Ishida ,  Takashi Nara ,  Hiroshi Kimura

IPC: G11B5/09 ,  G11B20/10 ,  G11B20/14 ,  H03H11/26 ,  H03H11/54 ,  H03K5/13 ,  H03K5/135 ,  H03L7/081 ,  H03L7/089 ,  H03L7/099 ,  H04L7/00 ,  H04L7/02

CPC classification number: H03L7/0805 ,  G11B20/10 ,  G11B20/1403 ,  H03K5/13 ,  H03L7/0812 ,  H03L7/0896 ,  H03L7/0995 ,  H04L7/02 ,  H04L7/0008 ,  H04L7/0041

Abstract: A signal processing delay circuit is fabricated as a semiconductor integration circuit to cope with increase in the data transfer speed and data recording and reproducing density on a recording medium. In the delay circuit, the amount of delay of a reference delay circuit of a delay PLL is controlled to take a fixed value independent of deviation in quality of the semiconductor circuit, change in power, and alteration in temperature. A control signal supervising the delay amount of the reference delay circuit is employed to control amounts of delay of input signals supplied to a window adjustment delay circuit of a window adjustment circuit and a T/2 generation delay circuit generating a synchronizing signal. Each of these delay circuits includes an analog variable delay circuit having the same configuration. The window adjustment delay circuit is supervised by a signal obtained by weighting the control signal by a D/A converter. A data acquisition circuit and a data write circuit each include an analog variable delay circuit.

Abstract translation: 制造信号处理延迟电路作为半导体积分电路，以应对数据传送速度的增加和记录介质上的数据记录和再现密度。 在延迟电路中，延迟PLL的参考延迟电路的延迟量被控制为独立于半导体电路的质量偏差，功率变化和温度变化的固定值。 采用监视参考延迟电路的延迟量的控制信号来控制提供给窗口调整电路的窗口调整延迟电路的输入信号的延迟量和产生同步信号的T / 2产生延迟电路。 这些延迟电路中的每一个包括具有相同配置的模拟可变延迟电路。 窗口调整延迟电路由通过D / A转换器对控制信号进行加权而获得的信号进行监视。 数据采集​​电路和数据写入电路各自包括模拟可变延迟电路。

公开(公告)号：US5625632A

公开(公告)日：1997-04-29

申请号：US319725

申请日：1994-10-07

Applicant: Yoshiteru Ishida ,  Kazunori Iwabuchi ,  Hideyuki Yamakawa ,  Hiromi Matsushige

Inventor： Yoshiteru Ishida ,  Kazunori Iwabuchi ,  Hideyuki Yamakawa ,  Hiromi Matsushige

IPC: G11B20/10 ,  G06F11/10 ,  H03M13/00

CPC classification number: G11B20/10009

Abstract: A data discrimination apparatus which is capable of correcting a decrease in amplitude of a signal to be data discriminated by a correction value so as to correct the bit itself which was used as a target bit to determine the correction value. A decision circuit preliminarily classifies an equalizer output into symbols "0" and "1" to obtain a run length of the symbol "0" with respect to a given symbol "1" (the target bit). A correction value generating circuit includes a memory device which contains correction values in correspondence with all the possible values of the run length, and outputs one of the correction values out of the memory device in response to an output from the decision circuit. A delay circuit delays the equalizer output by a time which is required until the correction value is output. An operation circuit adds the selected correction value to the delayed equalizer output, to correct the same. The thus corrected equalizer output is data discriminated in a data discrimination circuit, with a lowered error rate owing to the correction.

Abstract translation: 一种数据识别装置，其能够校正由校正值识别的要被数据的信号的幅度的降低，以便校正用作目标位的位本身以确定校正值。 判定电路预先将均衡器输出分类为符号“0”和“1”，以获得相对于给定符号“1”（目标位）的符号“0”的游程长度。 校正值产生电路包括存储器件，其存储与游程长度的所有可能值相对应的校正值，并且响应于来自判定电路的输出将一个校正值输出存储器件。 延迟电路使均衡器输出延迟所需的时间，直到校正值被输出。 操作电路将所选择的校正值与延迟均衡器输出相加，以校正相同的值。 这样校正的均衡器输出是在数据鉴别电路中鉴别的数据，由于校正而导致的误差率降低。

公开(公告)号：US20060227451A1

公开(公告)日：2006-10-12

申请号：US11400579

申请日：2006-04-07

Applicant: Naoki Satoh ,  Yoshiteru Ishida ,  Yoshiju Watanabe ,  Terumi Takashi

Inventor： Naoki Satoh ,  Yoshiteru Ishida ,  Yoshiju Watanabe ,  Terumi Takashi

IPC: G11B21/02 ,  G11B5/09 ,  G11B15/46

CPC classification number: G11B19/26

Abstract: Embodiments of the invention increase the convenience of a magnetic disk drive for portable use by shortening a period of time required to record a large amount of data, and by increasing the reproduction time, in the magnetic disk drive. In one embodiment, an area between servo data parts is interpolated by servo data parts, each of which stores a burst signal, so that the allocation density of a burst signal is made k times. At the time of write operation in which data is written, only the servo data parts are made use of to perform the servo control while a disk is driven at high rotational speed so as to reduce the recording time. At the time of read operation in which data is reproduced, the servo data parts are made use of to ensure the required precision of the servo control at low rotational speed that is 1/k of the rotational speed at the time of write operation. The reproduction at low rotational speed enables the reduction in power consumption.

公开(公告)号：US20060069845A1

公开(公告)日：2006-03-30

申请号：US11228776

申请日：2005-09-16

Applicant: Yoshiteru Ishida ,  Hitoshi Ogawa ,  Atsushi Saito ,  Terumi Takashi

Inventor： Yoshiteru Ishida ,  Hitoshi Ogawa ,  Atsushi Saito ,  Terumi Takashi

IPC: G06F12/00

CPC classification number: G11B19/04 ,  G11B20/10 ,  G11B27/036 ,  G11B27/322 ,  G11B2220/2516

Abstract: In one embodiment, a write/read apparatus includes an external interface section for data input; an external interface section for data output; a memory for temporarily storing the data that is input through the external interface section for data input and written on the recording medium and the data that is read from the recording medium and sent to the outside through the external interface section for data output; an address generating section for generating unique addresses associated with physical block addresses of the recording medium; a flag generating section for generating flags for prohibiting overwriting of the data to be written on the recording medium; and a processing section for adding the unique addresses generated in the address generating section to the data that is stored in the memory and that is to be written on the recording medium. The data with the addition of the flags generated in the flag generating section and the unique addresses is written on the recording medium.

公开(公告)号：US6104331A

公开(公告)日：2000-08-15

申请号：US161734

申请日：1998-09-29

Applicant: Yoshiteru Ishida ,  Naoki Satoh ,  Terumi Takashi ,  Akihiko Hirano ,  Seiichi Mita

Inventor： Yoshiteru Ishida ,  Naoki Satoh ,  Terumi Takashi ,  Akihiko Hirano ,  Seiichi Mita

IPC: G11B5/09 ,  G11B5/012 ,  G11B19/04 ,  G11B20/10 ,  G11B20/24 ,  G11B23/00 ,  H03M1/12 ,  G11B5/02

CPC classification number: G11B19/04 ,  G11B20/10009 ,  G11B20/24 ,  G11B5/012 ,  G11B23/0007 ,  G11B5/09

Abstract: A reproduced signal processing circuit includes a variable gain amplifier to which a signal read from a medium by a reproducing head is inputted; an analog-to-digital converter for converting a signal outputted from the variable gain amplifier into a digital signal; and a variable frequency oscillator for supplying an operation clock signal to the analog-to-digital converter. A reproduced signal processing method includes the steps of operating a first control loop for controlling the variable gain amplifier; operating at least either one of a second control loop and a third control loop, the second control loop controlling the variable frequency oscillator, the third control loop controlling the variable frequency oscillator; filtering by analog filter means the read signal inputted to the variable gain amplifier; operating at least one of first, second, and third noise detecting operations, the first noise detecting operation detecting presence or absence of a noise by comparing an amplitude of the output signal from the variable gain amplifier with a predetermined threshold value, the second noise detecting operation detecting a noise during an operation period of the second control loop, the third noise detecting operation detecting a noise during an operation period of the third control loop; and changing the range of cutoff frequency of the analog filter means in accordance with a result from at least one of the first, second, and third noise detecting operations, thereby controlling at least one of the first, second, and third control loops.

Abstract translation: 再现信号处理电路包括可变增益放大器，从再现头从介质读取的信号被输入到该可变增益放大器; 用于将从可变增益放大器输出的信号转换为数字信号的模拟 - 数字转换器; 以及用于向模数转换器提供操作时钟信号的可变频率振荡器。 再现信号处理方法包括以下步骤：操作用于控制可变增益放大器的第一控制环路; 操作第二控制回路和第三控制回路中的至少一个，控制可变频率振荡器的第二控制回路，控制可变频率振荡器的第三控制回路; 通过模拟滤波器滤波意味着输入到可变增益放大器的读取信号; 操作第一，第二和第三噪声检测操作中的至少一个，所述第一噪声检测操作通过将来自可变增益放大器的输出信号的幅度与预定阈值进行比较来检测噪声的存在或不存在，第二噪声检测 操作在第二控制回路的操作期间检测噪声，第三噪声检测操作在第三控制回路的操作期间检测噪声; 以及根据第一，第二和第三噪声检测操作中的至少一个的结果改变模拟滤波器装置的截止频率的范围，从而控制第一，第二和第三控制回路中的至少一个。

公开(公告)号：US5553104A

公开(公告)日：1996-09-03

申请号：US266779

申请日：1994-06-29

Applicant: Terumi Takashi ,  Akihiko Hirano ,  Kazunori Iwabuchi ,  Hideyuki Yamakawa ,  Yoshiteru Ishida ,  Kazuhisa Shiraishi ,  Kazutoshi Ashikawa

Inventor： Terumi Takashi ,  Akihiko Hirano ,  Kazunori Iwabuchi ,  Hideyuki Yamakawa ,  Yoshiteru Ishida ,  Kazuhisa Shiraishi ,  Kazutoshi Ashikawa

IPC: G11B20/14 ,  G11B27/30 ,  H03L7/06 ,  H03L7/081 ,  H03L7/099 ,  H03L7/183 ,  H04L7/033 ,  H03D3/24

CPC classification number: H03L7/0996 ,  G11B20/1403 ,  G11B27/30 ,  H03L7/081 ,  H03L7/183 ,  H04L7/0337

Abstract: A clock timing extraction circuit for use in an information recording/reproducing apparatus has a phase comparator for comparing the reproduced signal with a selected clock signal to generate a phase error signal, a clock signal generation circuit for adjusting frequency to cause the error signal to approach zero according to the phase error signal and outputting a plurality of clock signals having mutually different phase differences, a selection circuit for outputting one of the plurality of clock signals on the basis of a selection signal, a phase difference judgement circuit for determining one of the plurality of clock signals having a minimum phase error (Vdet) and generating a selection signal for selection of the clock signal having the minimum phase difference, and a freeze circuit for blocking an output of the phase comparator until the clock signal having the minimum phase error is selected. The information recording/reproducing apparatus has an AGC circuit for limiting an amplitude of a reproduced signal received from a recording medium, the aforementioned clock timing extraction circuit, and a decoder circuit. The clock timing extraction circuit extracts a clock signal from an output signal of the AGC circuit and the decoder decodes the output signal of the AGC circuit on the basis of the extracted clock signal.

Abstract translation: 用于信息记录/再现装置的时钟定时提取电路具有一个相位比较器，用于将再生信号与所选择的时钟信号进行比较以产生相位误差信号;时钟信号产生电路，用于调整频率以使误差信号接近 根据相位误差信号输出零，并输出具有相互不同的相位差的多个时钟信号，用于基于选择信号输出多个时钟信号中的一个的选择电路，用于确定其中之一的相位差判定电路 具有最小相位误差（Vdet）的多个时钟信号，并且产生用于选择具有最小相位差的时钟信号的选择信号，以及用于阻止相位比较器的输出的冻结电路，直到具有最小相位误差的时钟信号 被选中。 信息记录/重放装置具有用于限制从记录介质接收的再现信号的幅度的AGC电路，上述时钟定时提取电路和解码器电路。 时钟定时提取电路从AGC电路的输出信号中提取时钟信号，解码器根据所提取的时钟信号对AGC电路的输出信号进行解码。

公开(公告)号：US20090015960A1

公开(公告)日：2009-01-15

申请号：US12217075

申请日：2008-06-30

Applicant: Naoki Satoh ,  Yoshiteru Ishida ,  Yoshiju Watanabe ,  Terumi Takashi

Inventor： Naoki Satoh ,  Yoshiteru Ishida ,  Yoshiju Watanabe ,  Terumi Takashi

IPC: G11B15/46

CPC classification number: G11B19/26

Abstract: Embodiments of the invention increase the convenience of a magnetic disk drive for portable use by shortening a period of time required to record a large amount of data, and by increasing the reproduction time, in the magnetic disk drive. In one embodiment, an area between servo data parts is interpolated by servo data parts, each of which stores a burst signal, so that the allocation density of a burst signal is made k times. At the time of write operation in which data is written, only the servo data parts are made use of to perform the servo control while a disk is driven at high rotational speed so as to reduce the recording time. At the time of read operation in which data is reproduced, the servo data parts are made use of to ensure the required precision of the servo control at low rotational speed that is 1/k of the rotational speed at the time of write operation. The reproduction at low rotational speed enables the reduction in power consumption.

Abstract translation: 本发明的实施例通过缩短记录大量数据所需的时间周期以及通过增加磁盘驱动器中的再现时间来增加用于便携式使用的磁盘驱动器的便利性。 在一个实施例中，伺服数据部分之间的区域由伺服数据部分内插，每个伺服数据部分存储脉冲串信号，使得脉冲信号的分配密度为k次。 在写入数据的写入操作时，仅利用伺服数据部分来执行伺服控制，同时以高转速驱动盘，以便减少记录时间。 在再现数据的读取操作时，利用伺服数据部分来确保在写入操作时转速为1 / k的低转速下的伺服控制所要求的精度。 在低转速下的再现能够降低功耗。

公开(公告)号：US5448424A

公开(公告)日：1995-09-05

申请号：US196478

申请日：1994-02-15

Applicant: Akihiko Hirano ,  Terumi Takashi ,  Kazunori Iwabuchi ,  Hideyuki Yamakawa ,  Yoshiteru Ishida ,  Minoru Kosuge

Inventor： Akihiko Hirano ,  Terumi Takashi ,  Kazunori Iwabuchi ,  Hideyuki Yamakawa ,  Yoshiteru Ishida ,  Minoru Kosuge

IPC: G11B5/09 ,  G11B20/04 ,  G11B20/10 ,  G11B20/12 ,  G11B20/14 ,  H03G3/00 ,  H03G3/20 ,  H03G3/30 ,  H03G11/00 ,  G11B5/035

CPC classification number: G11B20/10055 ,  G11B20/10009 ,  G11B20/1403 ,  H03G3/001 ,  G11B20/1252

Abstract: An AGC circuit is provided with a variable gain amplifier which changes an amplification gain of an input signal in accordance with an instruction; an extraction unit for extracting a value of an output of the variable gain amplifier at a predetermined interval; and a variable gain control unit for instructing the amplification gain of the variable gain amplifier in a manner such that the amplitude of the input signal is equal to a predetermined amplitude on the basis of the value extracted by the extraction unit. The variable gain control unit is provided with an error signal output device for squaring the value extracted by the extraction unit and for generating an error signal to instruct the amplification gain of the variable gain amplifier in a manner such that the amplitude of the input signal is equal to a predetermined amplitude on the basis of the square value and a square value just before it; and an integrating device for integrating the error signal from the error signal output device and for instructing the amplification gain of the variable gain amplifier.

Abstract translation: AGC电路设置有根据指令改变输入信号的放大增益的可变增益放大器; 提取单元，用于以预定间隔提取可变增益放大器的输出值; 以及可变增益控制单元，用于以使得输入信号的幅度基于由提取单元提取的值等于预定幅度的方式来指示可变增益放大器的放大增益。 可变增益控制单元设置有误差信号输出装置，用于对由提取单元提取的值进行平方，并产生误差信号，以使得输入信号的振幅为 基于正方形值等于预定幅度和刚好在其前的平方值; 以及用于积分来自误差信号输出装置的误差信号并用于指示可变增益放大器的放大增益的积分装置。