公开(公告)号：US07235440B2

公开(公告)日：2007-06-26

申请号：US10630969

申请日：2003-07-31

申请人： David L O'Meara ,  Cory Wajda ,  Anthony Dip ,  Michael Toeller ,  Toshihara Furukawa ,  Kristen Scheer ,  Alessandro Callegari ,  Fred Buehrer ,  Sufi Zafar ,  Evgeni Gousev ,  Anthony Chou ,  Paul Higgins

发明人： David L O'Meara ,  Cory Wajda ,  Anthony Dip ,  Michael Toeller ,  Toshihara Furukawa ,  Kristen Scheer ,  Alessandro Callegari ,  Fred Buehrer ,  Sufi Zafar ,  Evgeni Gousev ,  Anthony Chou ,  Paul Higgins

IPC分类号： H01L21/8242

CPC分类号： H01L21/28194 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/28167 ,  H01L21/28202 ,  H01L21/28211 ,  H01L21/3144 ,  H01L21/31604 ,  H01L21/31616 ,  H01L21/31637 ,  H01L21/31641 ,  H01L21/31645 ,  H01L21/31662 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518

摘要： Ultra-thin oxide layers are formed utilizing low pressure processing to achieve self-limiting oxidation of substrates and provide ultra-thin oxide. The substrates to be processed can contain an initial dielectric layer such as an oxide layer, an oxynitride layer, a nitride layer, a high-k layer, or alternatively can lack an initial dielectric layer. The processing can be carried out using a batch type process chamber or, alternatively, using a single-wafer process chamber. One embodiment of the invention provides self-limiting oxidation of Si-substrates that results in SiO2 layers with a thickness of about 15 A, where the thickness of the SiO2 layers varies less than about 1 A over the substrates.

摘要翻译： 使用低压处理形成超薄氧化层，以实现衬底的自限制氧化并提供超薄氧化物。 待处理的基板可以包含初始介电层，例如氧化物层，氧氮化物层，氮化物层，高k层，或者可以缺少初始介电层。 处理可以使用间歇式处理室进行，或者使用单晶圆处理室进行。 本发明的一个实施例提供了Si衬底的自限制氧化，其导致厚度为约15A的SiO 2层，其中SiO 2层的厚度 在基材上变化小于约1A。

公开(公告)号：US07202186B2

公开(公告)日：2007-04-10

申请号：US10630970

申请日：2003-07-31

申请人： David L O'Meara ,  Cory Wajda ,  Anthony Dip ,  Michael Toeller ,  Toshihara Furukawa ,  Kristen Scheer ,  Alessandro Callegari ,  Fred Buehrer ,  Sufi Zafar ,  Evgeni Gousev ,  Anthony Chou ,  Paul Higgins

发明人： David L O'Meara ,  Cory Wajda ,  Anthony Dip ,  Michael Toeller ,  Toshihara Furukawa ,  Kristen Scheer ,  Alessandro Callegari ,  Fred Buehrer ,  Sufi Zafar ,  Evgeni Gousev ,  Anthony Chou ,  Paul Higgins

IPC分类号： H01L21/31 ,  H01L21/469

CPC分类号： H01L21/28185 ,  C23C16/308 ,  H01L21/0214 ,  H01L21/02238 ,  H01L21/02249 ,  H01L21/02255 ,  H01L21/28202 ,  H01L21/3144 ,  H01L21/31604 ,  H01L21/31616 ,  H01L21/31637 ,  H01L21/31641 ,  H01L21/31645 ,  H01L21/31662 ,  H01L21/67098 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518

摘要： Ultra-thin oxynitride layers are formed utilizing low-pressure processing to achieve self-limiting oxidation of substrates and provide ultra-thin oxynitride. The substrates to be processed can contain an initial dielectric layer such as an oxide layer, an oxynitride layer, or a nitride layer, or alternatively can lack an initial dielectric layer. The processing can be carried out using a batch type process chamber or a single-wafer process chamber.

摘要翻译： 使用低压处理形成超薄氧氮化物层，以实现衬底的自限制氧化并提供超薄氧氮化物。 要处理的基板可以包含初始介电层，例如氧化物层，氧氮化物层或氮化物层，或者可以缺少初始介电层。 处理可以使用间歇式处理室或单晶片处理室进行。

公开(公告)号：US20050026453A1

公开(公告)日：2005-02-03

申请号：US10630969

申请日：2003-07-31

申请人： David O'Meara ,  Cory Wajda ,  Anthony Dip ,  Michael Toeller ,  Toshihara Furukawa ,  Kristen Scheer ,  Alessandro Callegari ,  Fred Buehrer ,  Sufi Zafar ,  Evgeni Gousev ,  Anthony Chou ,  Paul Higgins

发明人： David O'Meara ,  Cory Wajda ,  Anthony Dip ,  Michael Toeller ,  Toshihara Furukawa ,  Kristen Scheer ,  Alessandro Callegari ,  Fred Buehrer ,  Sufi Zafar ,  Evgeni Gousev ,  Anthony Chou ,  Paul Higgins

IPC分类号： H01L21/28 ,  H01L21/314 ,  H01L21/316 ,  H01L29/51 ,  H01L21/31

CPC分类号： H01L21/28194 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/28167 ,  H01L21/28202 ,  H01L21/28211 ,  H01L21/3144 ,  H01L21/31604 ,  H01L21/31616 ,  H01L21/31637 ,  H01L21/31641 ,  H01L21/31645 ,  H01L21/31662 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518

摘要： Ultra-thin oxide layers are formed utilizing low pressure processing to achieve self-limiting oxidation of substrates and provide ultra-thin oxide. The substrates to be processed can contain an initial dielectric layer such as an oxide layer, an oxynitride layer, a nitride layer, a high-k layer, or alternatively can lack an initial dielectric layer. The processing can be carried out using a batch type process chamber or, alternatively, using a single-wafer process chamber. One embodiment of the invention provides self-limiting oxidation of Si-substrates that results in SiO2 layers with a thickness of about 15 A, where the thickness of the SiO2 layers varies less than about 1 A over the substrates.

摘要翻译： 使用低压处理形成超薄氧化层，以实现衬底的自限制氧化并提供超薄氧化物。 待处理的基板可以包含初始介电层，例如氧化物层，氧氮化物层，氮化物层，高k层，或者可以缺少初始介电层。 处理可以使用间歇式处理室进行，或者使用单晶圆处理室进行。 本发明的一个实施例提供Si衬底的自限制氧化，其导致厚度为约15A的SiO 2层，其中SiO 2层的厚度在衬底上变化小于约1A。

公开(公告)号：US20050026459A1

公开(公告)日：2005-02-03

申请号：US10630970

申请日：2003-07-31

申请人： David O'Meara ,  Cory Wajda ,  Anthony Dip ,  Michael Toeller ,  Toshihara Furukawa ,  Kristen Scheer ,  Alessandro Callegari ,  Fred Buehrer ,  Sufi Zafar ,  Evgeni Gousev ,  Anthony Chou ,  Paul Higgins

发明人： David O'Meara ,  Cory Wajda ,  Anthony Dip ,  Michael Toeller ,  Toshihara Furukawa ,  Kristen Scheer ,  Alessandro Callegari ,  Fred Buehrer ,  Sufi Zafar ,  Evgeni Gousev ,  Anthony Chou ,  Paul Higgins

IPC分类号： C23C16/30 ,  H01L21/00 ,  H01L21/28 ,  H01L21/314 ,  H01L21/316 ,  H01L29/51 ,  H01L21/31 ,  H01L21/469

CPC分类号： H01L21/28185 ,  C23C16/308 ,  H01L21/0214 ,  H01L21/02238 ,  H01L21/02249 ,  H01L21/02255 ,  H01L21/28202 ,  H01L21/3144 ,  H01L21/31604 ,  H01L21/31616 ,  H01L21/31637 ,  H01L21/31641 ,  H01L21/31645 ,  H01L21/31662 ,  H01L21/67098 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518

摘要： Ultra-thin oxynitride layers are formed utilizing low-pressure processing to achieve self-limiting oxidation of substrates and provide ultra-thin oxynitride. The substrates to be processed can contain an initial dielectric layer such as an oxide layer, an oxynitride layer, or a nitride layer, or alternatively can lack an initial dielectric layer. The processing can be carried out using a batch type process chamber or a single-wafer process chamber.

摘要翻译： 使用低压处理形成超薄氧氮化物层，以实现衬底的自限制氧化并提供超薄氧氮化物。 要处理的基板可以包含初始介电层，例如氧化物层，氧氮化物层或氮化物层，或者可以缺少初始介电层。 处理可以使用间歇式处理室或单晶片处理室进行。

公开(公告)号：US20060289903A1

公开(公告)日：2006-12-28

申请号：US11513101

申请日：2006-08-30

申请人： Wanda Andreoni ,  Alessandro Callegari ,  Eduard Cartier ,  Alessandro Curioni ,  Christopher D'Emic ,  Evgeni Gousev ,  Michael Gribelyuk ,  Paul Jamison ,  Rajarao Jammy ,  Dianne Lacey ,  Fenton McFeely ,  Vijay Narayanan ,  Carlo Pignedoli ,  Joseph Shepard ,  Sufi Zafar

发明人： Wanda Andreoni ,  Alessandro Callegari ,  Eduard Cartier ,  Alessandro Curioni ,  Christopher D'Emic ,  Evgeni Gousev ,  Michael Gribelyuk ,  Paul Jamison ,  Rajarao Jammy ,  Dianne Lacey ,  Fenton McFeely ,  Vijay Narayanan ,  Carlo Pignedoli ,  Joseph Shepard ,  Sufi Zafar

IPC分类号： H01L31/112 ,  H01L29/80

CPC分类号： H01L21/28176 ,  H01L29/4908 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/6656 ,  H01L29/66575 ,  H01L29/66772 ,  H01L29/7833 ,  H01L29/78684

摘要： The present invention provides a gate stack structure that has high mobilites and low interfacial charges as well as semiconductor devices, i.e., metal oxide semiconductor field effect transistors (MOSFETs) that include the same. In the semiconductor devices, the gate stack structure of the present invention is located between the substrate and an overlaying gate conductor. The present invention also provides a method of fabricating the inventive gate stack structure in which a high temperature annealing process (on the order of about 800° C.) is employed. The high temperature anneal used in the present invention provides a gate stack structure that has an interface state density, as measured by charge pumping, of about 8×1010 charges/cm2 or less, a peak mobility of about 250 cm2/V-s or greater and substantially no mobility degradation at about 6.0×1012 inversion charges/cm2 or greater.

摘要翻译： 本发明提供具有高移动性和低界面电荷的栅堆叠结构，以及包括其的半导体器件，即金属氧化物半导体场效应晶体管（MOSFET）。 在半导体器件中，本发明的栅极堆叠结构位于衬底和覆盖栅极导体之间​​。 本发明还提供一种制造本发明的栅叠层结构的方法，其中采用了高温退火工艺（大约800℃）。 在本发明中使用的高温退火提供了一种栅堆叠结构，其具有通过电荷泵浦测量的约8×10 10电荷/ cm 2的界面态密度或 更少，约250cm 2 / Vs或更高的峰迁移率，并且在约6.0×10 12反转电荷/ cm 2处基本上没有迁移率降解， 或更大。

公开(公告)号：US08153514B2

公开(公告)日：2012-04-10

申请号：US12187767

申请日：2008-08-07

申请人： Wanda Andreoni ,  Alessandro C. Callegari ,  Eduard A. Cartier ,  Alessandro Curioni ,  Christopher P. D'Emic ,  Evgeni Gousev ,  Michael A. Gribelyuk ,  Paul C. Jamison ,  Rajarao Jammy ,  Dianne L. Lacey ,  Fenton R. McFeely ,  Vijay Narayanan ,  Carlo A. Pignedoli ,  Joseph F. Shepard, Jr. ,  Sufi Zafar

发明人： Wanda Andreoni ,  Alessandro C. Callegari ,  Eduard A. Cartier ,  Alessandro Curioni ,  Christopher P. D'Emic ,  Evgeni Gousev ,  Michael A. Gribelyuk ,  Paul C. Jamison ,  Rajarao Jammy ,  Dianne L. Lacey ,  Fenton R. McFeely ,  Vijay Narayanan ,  Carlo A. Pignedoli ,  Joseph F. Shepard, Jr. ,  Sufi Zafar

IPC分类号： H01L21/3205

CPC分类号： H01L21/28176 ,  H01L29/4908 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/6656 ,  H01L29/66575 ,  H01L29/66772 ,  H01L29/7833 ,  H01L29/78684

摘要： The present invention provides a gate stack structure that has high mobilities and low interfacial charges as well as semiconductor devices, i.e., metal oxide semiconductor field effect transistors (MOSFETs) that include the same. In the semiconductor devices, the gate stack structure of the present invention is located between the substrate and an overlaying gate conductor. The present invention also provides a method of fabricating the inventive gate stack structure in which a high temperature annealing process (on the order of about 800° C.) is employed. The high temperature anneal used in the present invention provides a gate stack structure that has an interface state density, as measured by charge pumping, of about 8×1010 charges/cm2 or less, a peak mobility of about 250 cm2V-s or greater and substantially no mobility degradation at about 6.0×1012 inversion charges/cm2 or greater.

摘要翻译： 本发明提供具有高迁移率和低界面电荷的栅叠层结构，以及包括其的半导体器件即金属氧化物半导体场效应晶体管（MOSFET）。 在半导体器件中，本发明的栅极堆叠结构位于衬底和覆盖栅极导体之间​​。 本发明还提供一种制造本发明的栅叠层结构的方法，其中采用了高温退火工艺（大约800℃）。 本发明中使用的高温退火提供了一种栅极叠层结构，其具有约8×10 10电荷/ cm 2或更小的峰值迁移率，约250cm 2 / s或更大的峰迁移率的通过电荷泵浦测量的界面状态密度，以及 在大约6.0×10 12反转电荷/ cm 2或更大时基本上没有迁移率降解。

公开(公告)号：US20080293259A1

公开(公告)日：2008-11-27

申请号：US12187767

申请日：2008-08-07

申请人： Wanda Andreoni ,  Alessandro C. Callegari ,  Eduard A. Cartier ,  Alessandro Curioni ,  Christopher P. D'Emic ,  Evgeni Gousev ,  Michael A. Gribelyuk ,  Paul C. Jamison ,  Rajarao Jammy ,  Dianne L. Lacey ,  Fenton R. McFeely ,  Vijay Narayanan ,  Carlo A. Pignedoli ,  Joseph F. Shepard, JR. ,  Sufi Zafar

发明人： Wanda Andreoni ,  Alessandro C. Callegari ,  Eduard A. Cartier ,  Alessandro Curioni ,  Christopher P. D'Emic ,  Evgeni Gousev ,  Michael A. Gribelyuk ,  Paul C. Jamison ,  Rajarao Jammy ,  Dianne L. Lacey ,  Fenton R. McFeely ,  Vijay Narayanan ,  Carlo A. Pignedoli ,  Joseph F. Shepard, JR. ,  Sufi Zafar

IPC分类号： H01L21/263

CPC分类号： H01L21/28176 ,  H01L29/4908 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/6656 ,  H01L29/66575 ,  H01L29/66772 ,  H01L29/7833 ,  H01L29/78684

摘要： The present invention provides a gate stack structure that has high mobilities and low interfacial charges as well as semiconductor devices, i.e., metal oxide semiconductor field effect transistors (MOSFETs) that include the same. In the semiconductor devices, the gate stack structure of the present invention is located between the substrate and an overlaying gate conductor. The present invention also provides a method of fabricating the inventive gate stack structure in which a high temperature annealing process (on the order of about 800° C.) is employed. The high temperature anneal used in the present invention provides a gate stack structure that has an interface state density, as measured by charge pumping, of about 8×1010 charges/cm2 or less, a peak mobility of about 250 cm2V-s or greater and substantially no mobility degradation at about 6.0×1012 inversion charges/cm2 or greater.

摘要翻译： 本发明提供具有高移动性和低界面电荷的栅叠层结构，以及包括其的半导体器件，即金属氧化物半导体场效应晶体管（MOSFET）。 在半导体器件中，本发明的栅极堆叠结构位于衬底和覆盖栅极导体之间​​。 本发明还提供一种制造本发明的栅叠层结构的方法，其中采用了高温退火工艺（大约800℃）。 本发明中使用的高温退火提供了具有大约8×10 10电荷/ cm 2或更小的电荷泵浦的界面状态密度，约250cm 2 / s以上的峰值迁移率和基本上没有 约6.0×10 12反相电荷/ cm 2以上的迁移率降解。

公开(公告)号：US20050082624A1

公开(公告)日：2005-04-21

申请号：US10689222

申请日：2003-10-20

申请人： Evgeni Gousev ,  Alessandro Callegari ,  Dianne Lacey ,  Deborah Neumayer ,  Huiling Shang

发明人： Evgeni Gousev ,  Alessandro Callegari ,  Dianne Lacey ,  Deborah Neumayer ,  Huiling Shang

IPC分类号： H01L21/28 ,  H01L21/316 ,  H01L29/51 ,  H01L29/94

CPC分类号： H01L21/28194 ,  H01L21/02112 ,  H01L21/02271 ,  H01L21/0228 ,  H01L21/28264 ,  H01L21/31604 ,  H01L29/517 ,  H01L29/518

摘要： A structure, and method of fabrication, for high performance semiconductor field effect devices is disclosed. These devices are having a gate dielectric containing a germanate material. In representative embodiments the gate dielectric is essentially a layer of a germanate material. The chemical composition of such materials is MezGexOy, where Me stands for a metal with high ion polarizability, and x, y, and z are non-zero integers. Such a gate dielectric is advantageous, from the point of view of dielectric constant, barrier height, carrier mobility, thermal stability, and interface stability.

摘要翻译： 公开了一种用于高性能半导体场效应器件的结构和制造方法。 这些器件具有含有锗酸盐材料的栅极电介质。 在代表性的实施例中，栅极电介质基本上是锗酸盐材料层。 这种材料的化学成分是Me z O x O x O y，其中Me代表具有高离子极化率的金属，x，y ，z是非零整数。 从介电常数，势垒高度，载流子迁移率，热稳定性和界面稳定性的观点来看，这种栅极电介质是有利的。

公开(公告)号：US20120274647A1

公开(公告)日：2012-11-01

申请号：US13094687

申请日：2011-04-26

申请人： Je-Hsiung Lan ,  Sang-June Park ,  Jonghae Kim ,  Evgeni Gousev ,  Matthew Nowak ,  Philip J. Stephanou ,  Justin Black ,  Kurt Petersen ,  Srinivasan Ganapathi

发明人： Je-Hsiung Lan ,  Sang-June Park ,  Jonghae Kim ,  Evgeni Gousev ,  Matthew Nowak ,  Philip J. Stephanou ,  Justin Black ,  Kurt Petersen ,  Srinivasan Ganapathi

IPC分类号： H01L41/053 ,  G09G5/39 ,  H01L41/22 ,  G06T1/60

CPC分类号： H03H3/0072 ,  H03H9/2447 ,  Y10T29/42

摘要： This disclosure provides implementations of electromechanical systems resonator structures, devices, apparatus, systems, and related processes. In one aspect, a sacrificial layer is deposited on an insulating substrate. A lower electrode layer is formed proximate the sacrificial layer. A piezoelectric layer is deposited on the lower electrode layer. An upper electrode layer is formed on the piezoelectric layer. At least a portion of the sacrificial layer is removed to define a cavity such that at least a portion of the lower electrode layer is spaced apart from the insulating substrate.

摘要翻译： 本公开提供了机电系统谐振器结构，设备，装置，系统和相关过程的实现。 在一个方面，牺牲层沉积在绝缘衬底上。 在牺牲层附近形成下电极层。 压电层沉积在下电极层上。 在压电层上形成上电极层。 去除牺牲层的至少一部分以限定空腔，使得下电极层的至少一部分与绝缘基板间隔开。

公开(公告)号：US20120206462A1

公开(公告)日：2012-08-16

申请号：US13453844

申请日：2012-04-23

申请人： Ana R. Londergan ,  Bangalore R. Natarajan ,  Evgeni Gousev ,  James Randolph Webster ,  David Heald

发明人： Ana R. Londergan ,  Bangalore R. Natarajan ,  Evgeni Gousev ,  James Randolph Webster ,  David Heald

IPC分类号： G02B26/00 ,  B05D5/06 ,  G06T1/00

CPC分类号： G02B26/001 ,  B81B3/0008 ,  B81B2201/047

摘要： Devices, methods, and systems comprising a MEMS device, for example, an interferometric modulator, that comprises a cavity in which a layer coats multiple surfaces. The layer is conformal or non-conformal. In some embodiments, the layer is formed by atomic layer deposition (ALD). Preferably, the layer comprises a dielectric material. In some embodiments, the MEMS device also exhibits improved characteristics, such as improved electrical insulation between moving electrodes, reduced stiction, and/or improved mechanical properties.

摘要翻译： 包括MEMS器件（例如干涉式调制器）的器件，方法和系统，其包括其中层涂覆多个表面的空腔。 该层是保形的或非保形的。 在一些实施例中，该层由原子层沉积（ALD）形成。 优选地，该层包括电介质材料。 在一些实施例中，MEMS器件还表现出改进的特性，例如移动电极之间的改善的电绝缘性，降低的静摩擦力和/或改善的机械性能。