-
公开(公告)号：US10403587B2
公开(公告)日：2019-09-03
申请号：US15945778
申请日：2018-04-05
Applicant: FUJITSU LIMITED
Inventor： Masaru Sato , Yukiyasu Furukawa
IPC: H01L23/66 , H01L23/492 , H01L23/498 , H01L21/48 , H01L25/065 , H01L25/00 , H01Q1/22 , H01Q1/48 , H01L23/049
Abstract: A radio frequency circuit includes, a multilayer substrate having a grounded base metal and a plurality of insulating layers and wiring layers formed over the grounded base metal and having a recess surrounded by the plurality of insulating layers and wiring layers over the grounded base metal, an upper substrate having a through-hole penetrating the upper substrate, a first semiconductor chip mounted on the upper surface of the upper substrate and electrically coupled to a metal film formed on the lower surface of the upper substrate, a metal pillar formed on the upper surface of the grounded base metal in the recess, and a solder buried in the through-hole and bonded to the metal film and the upper surface of the metal pillar. The metal film is bonded to a ground wiring layer electrically coupled to the grounded base metal among the plurality of wiring layers.
-
公开(公告)号：US20190207574A1
公开(公告)日：2019-07-04
申请号：US16177552
申请日：2018-11-01
Applicant: FUJITSU LIMITED
Inventor： Naoko Kurahashi , Masaru Sato
CPC classification number: H03F3/601 , H03F3/193 , H03F3/245 , H03F2200/255 , H03F2200/423 , H03F2200/543
Abstract: An amplifier includes amplification stages connected in parallel between an input point and an output point and a feedback circuit, wherein the amplification stages each include a transistor configured to amplify a signal supplied from the input point, a harmonic processing unit configured to process harmonics present in an amplified signal output from an output node of the transistor, a connection point between the output node and the harmonic processing unit, and a transmission line connecting the connection point and the output point, wherein the feedback circuit feeds back a signal at the output point or a midway point of the transmission line of a given one of the amplification stages to a first end of a resistor connected to the connection point of the given one of the amplification stages, a second end of the resistor being connected to the connection point of another one of the amplification stages.
-
公开(公告)号：US09614485B2
公开(公告)日：2017-04-04
申请号：US14571734
申请日：2014-12-16
Applicant: FUJITSU LIMITED
Inventor： Masaru Sato
CPC classification number: H03F3/605 , H03F1/56 , H03F3/607 , H03F2200/222 , H03F2200/387 , H03F2200/451
Abstract: An amplifier circuit includes: plural transistors; plural first transmission lines respectively connected between input terminals of the plural transistors; plural second transmission lines respectively connected between output terminals of the plural transistors; an input node connected to the input terminal of a first stage transistor among the plural transistors; an output node connected to the output terminal of a final stage transistor among the plural transistors; and a capacitance connected to the output terminal of the first stage transistor via a third transmission line.
-
公开(公告)号：US09559643B2
公开(公告)日：2017-01-31
申请号：US14474640
申请日：2014-09-02
Applicant: FUJITSU LIMITED
Inventor： Masaru Sato
CPC classification number: H03F3/193 , H03F3/607 , H03F2200/09
Abstract: An amplifier circuit includes: first and second nodes configured to receive input of differential signals; third and fourth nodes; a plurality of first inductors configured to be connected in series between the first and second nodes; a plurality of second inductors configured to be connected in series between the third and fourth nodes; a plurality of field effect transistors configured to have gates each configured to be connected between the plurality of first inductors, sources each configured to be connected to a reference potential node, and drains each configured to be connected between the plurality of second inductors; and a synthesizing unit configured to synthesize signals at the third and fourth nodes.
Abstract translation: 放大器电路包括：被配置为接收差分信号的输入的第一和第二节点; 第三和第四个节点; 多个第一电感器，被配置为串联连接在第一和第二节点之间; 多个第二电感器，被配置为串联连接在第三和第四节点之间; 多个场效应晶体管被配置为具有各自被配置为连接在所述多个第一电感器之间的栅极，各个被配置为连接到参考电位节点的源以及被配置为连接在所述多个第二电感器之间的各个漏极; 以及合成单元，被配置为在第三和第四节点处合成信号。
-
公开(公告)号：US09490748B2
公开(公告)日：2016-11-08
申请号：US14164390
申请日：2014-01-27
Applicant: FUJITSU LIMITED
Inventor： Masaru Sato
CPC classification number: H03D1/10 , H03D7/02 , H03D7/165 , H03G3/3052
Abstract: A receiving device includes a dividing circuit, N pieces of internal circuits, and an averaging circuit. The dividing circuit is configured to divide an input signal into N pieces of divided signals (where N is an integer of two or larger), and the N pieces of internal circuits are configured to receive and process the N pieces of divided signals. The averaging circuit is configured to receive N pieces of output signals from the N pieces of internal circuits, averaging the output signals, and output an averaged signal.
Abstract translation: 接收装置包括分频电路，N个内部电路和平均电路。 分频电路被配置为将输入信号划分为N个分割信号（其中N是2或更大的整数），并且N个内部电路被配置为接收和处理N个分割信号。 平均电路被配置为从N个内部电路接收N个输出信号，对输出信号进行平均，并输出平均的信号。
-
Patent Agency Ranking
公开(公告)号：US08988150B2
公开(公告)日：2015-03-24
申请号：US13740246
申请日：2013-01-13
Applicant: Fujitsu Limited
Inventor： Masaru Sato
Abstract: An amplifier includes a transformer including a primary coil whose one end is connected to an input port and whose other end is connected to reference potential and a secondary coil magnetically-coupled with the primary coil, and a transistor including a source connected to one end of the secondary coil and a gate connected to other end of the secondary coil and a drain connected to an output port side.
Abstract translation: 放大器包括：变压器，其包括一端连接到输入端口并且另一端连接到参考电位的初级线圈和与初级线圈磁耦合的次级线圈;以及晶体管，其包括源极的一端 次级线圈和连接到次级线圈的另一端的栅极以及连接到输出端口侧的漏极。
-
公开(公告)号：US20160261237A1
公开(公告)日：2016-09-08
申请号：US15045860
申请日：2016-02-17
Applicant: FUJITSU LIMITED
Inventor： Masaru Sato , Naoko Kurahashi
CPC classification number: H03F1/0205 , H03F1/0288 , H03F1/07 , H03F1/18 , H03F1/42 , H03F1/56 , H03F3/193 , H03F3/195 , H03F3/604 , H03F3/607 , H03F3/72 , H03F2200/27 , H03F2200/315 , H03F2200/36 , H03F2200/42 , H03F2200/423 , H03F2200/451 , H03F2200/48 , H03F2200/519 , H03F2200/555 , H03F2200/75 , H03F2203/7227
Abstract: A distributed amplifier includes: an input-side transmission line; M amplification circuits; M output-side transmission lines; and a combination circuit configured to combine outputs of the M output-side transmission lines; wherein the input-side transmission line has an input-side serial line formed by connecting in series MxN unit transmission lines each including the same line length, and an input-side terminating resistor, the M amplification circuits each includes N amplifiers and the N amplifiers of the i-th amplification circuit take the input node of the ((k−1) M+i)-th input-side transmission line to be the input, and the output-side transmission line includes an output-side serial line including N transmission lines each being connected in series between the neighboring outputs of the N amplifiers and each having a line width in which the phase of the output of the amplifier in each stage agrees with one another.
Abstract translation: 分布式放大器包括：输入侧传输线; M放大电路; M输出侧传输线; 以及组合电路，被配置为组合M个输出侧传输线的输出; 其中输入侧传输线具有通过串联连接包括相同线路长度的M×N个单元传输线和输入侧终端电阻而形成的输入侧串行线，M个放大电路各自包括N个放大器和N个放大器 将第（（k-1）M + i个）输入侧传输线的输入节点作为输入，并且输出侧传输线包括输出侧串行线，包括 N个传输线各自串联连接在N个放大器的相邻输出之间，并且每个具有线宽度，其中每个级中的放大器的输出的相位彼此一致。
-
公开(公告)号：US09252078B2
公开(公告)日：2016-02-02
申请号：US14172020
申请日：2014-02-04
Applicant: FUJITSU LIMITED
Inventor： Toshihide Suzuki , Masaru Sato
IPC: H01L23/34 , H01L23/48 , H01L23/522 , H01L23/66
CPC classification number: H01L23/481 , H01L23/5223 , H01L23/5225 , H01L23/66 , H01L2924/0002 , H01L2924/00
Abstract: A semiconductor device includes a first electrode formed on a substrate, the first electrode being a first electrical potential; and a second electrode formed on the first electrode, the second electrode including a signal wiring that transmits a signal and a planar electrode part with a prescribed area. A shape of the first electrode corresponding to the planar electrode part is made into a slit shape such that a longitudinal direction of a slit is parallel to a direction in which the signal proceeds in the planar electrode part.
Abstract translation: 半导体器件包括形成在衬底上的第一电极，第一电极是第一电位; 以及形成在所述第一电极上的第二电极，所述第二电极包括发送信号的信号线和具有规定区域的平面电极部。 对应于平面电极部分的第一电极的形状被制成狭缝形状，使得狭缝的纵向方向平行于在平面电极部分中信号进行的方向。
-
9.发明授权Variable phase shifter, semiconductor integrated circuit and phase shifting method 有权可变移相器，半导体集成电路和相移方法公开(公告)号：US09106180B2
公开(公告)日：2015-08-11
申请号：US14029040
申请日：2013-09-17
Applicant: FUJITSU LIMITED
Inventor： Masaru Sato
Abstract: A variable phase shifter. The variable phase shifter includes: a transmission line that outputs quadrature signals from a pair of output ports in response to an input signal of a specific frequency; a synthesizer that includes a first transistor connected to a first port of the pair of output ports and a second transistor connected to a second port of the pair of output ports, and that on input of the input signal takes signals output from the pair of output ports of the transmission line with a phase according to their respective load impedances and employs the first and the second transistors to amplify and combine the signals; and a phase controller that controls the phase of the output signal that is combined and output by the synthesizer by controlling the amplification operation of each of the first and second transistors of the synthesizer.
Abstract translation: 可变移相器。 可变移相器包括：响应于特定频率的输入信号从一对输出端口输出正交信号的传输线; 合成器，其包括连接到所述一对输出端口的第一端口的第一晶体管和连接到所述一对输出端口的第二端口的第二晶体管，并且在所述输入信号的输入端从所述一对输出端输出的信号 传输线的端口根据其相应的负载阻抗具有相位，并且采用第一和第二晶体管来放大和组合信号; 以及相位控制器，其通过控制合成器的第一和第二晶体管的放大操作来控制由合成器组合和输出的输出信号的相位。
-
10.发明申请公开(公告)号：US20180315721A1
公开(公告)日：2018-11-01
申请号：US15945778
申请日：2018-04-05
Applicant: FUJITSU LIMITED
Inventor： Masaru Sato , Yukiyasu Furukawa
IPC: H01L23/66 , H01L23/049 , H01L23/492 , H01L23/498 , H01L21/48 , H01L25/065 , H01L25/00 , H01Q1/22 , H01Q1/48
CPC classification number: H01L23/66 , H01L21/4817 , H01L21/4853 , H01L21/4857 , H01L21/486 , H01L21/4875 , H01L23/04 , H01L23/041 , H01L23/043 , H01L23/049 , H01L23/055 , H01L23/492 , H01L23/49822 , H01L23/49827 , H01L23/49838 , H01L25/0657 , H01L25/50 , H01L2223/6611 , H01L2223/6616 , H01L2223/6677 , H01L2223/6683 , H01L2224/48091 , H01L2224/48227 , H01L2225/0651 , H01L2225/06548 , H01L2225/06572 , H01L2924/15192 , H01L2924/16195 , H01Q1/2283 , H01Q1/48 , H01L2924/00014
Abstract: A radio frequency circuit includes, a multilayer substrate having a grounded base metal and a plurality of insulating layers and wiring layers formed over the grounded base metal and having a recess surrounded by the plurality of insulating layers and wiring layers over the grounded base metal, an upper substrate having a through-hole penetrating the upper substrate, a first semiconductor chip mounted on the upper surface of the upper substrate and electrically coupled to a metal film formed on the lower surface of the upper substrate, a metal pillar formed on the upper surface of the grounded base metal in the recess, and a solder buried in the through-hole and bonded to the metal film and the upper surface of the metal pillar. The metal film is bonded to a ground wiring layer electrically coupled to the grounded base metal among the plurality of wiring layers.
-
-
-
-
-
-
-
-
-
Search Results
17
records
(took 0.014 seconds)
