公开(公告)号：US10658363B2

公开(公告)日：2020-05-19

申请号：US16562481

申请日：2019-09-06

Applicant: GLOBALFOUNDRIES INC.

Inventor： Balaji Kannan ,  Ayse M. Ozbek ,  Tao Chu ,  Bala Haran ,  Vishal Chhabra ,  Katsunori Onishi ,  Guowei Xu

IPC: H01L27/092 ,  H01L29/06 ,  H01L27/02 ,  H01L21/311 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/027 ,  H01L21/8238 ,  H01L29/51 ,  H01L27/11

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a cut inside a replacement metal gate trench to mitigate n-p proximity effects and methods of manufacture. The structure described herein includes: a first device; a second device, adjacent to the first device; a dielectric material, of the first device and the second device, including a cut within a trench between the first device and the second device; and a common gate electrode shared with the first device and the second device, the common gate electrode provided over the dielectric material and contacting underlying material within the cut.

公开(公告)号：US20180261595A1

公开(公告)日：2018-09-13

申请号：US15455313

申请日：2017-03-10

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Katsunori Onishi ,  Tek Po Rinus Lee

IPC: H01L27/088 ,  H01L21/8234 ,  H01L21/311 ,  H01L29/66 ,  H01L29/423

CPC classification number: H01L27/0886 ,  H01L21/31116 ,  H01L21/823431 ,  H01L21/823456 ,  H01L21/823468 ,  H01L21/823475 ,  H01L29/42376 ,  H01L29/66545

Abstract: A method includes forming a first plurality of gate structures. A second plurality of gate structures is formed. A first spacer is formed on each of the first and second pluralities of gate structures. A first cavity is defined between the first spacers of a first pair of the first plurality of gate structures. A second cavity is defined between the first spacers of a second pair of the second plurality of gate structures. A second spacer is selectively formed in the second cavity on the first spacer of each of the gate structures of the second pair without forming the second spacer in the first cavity. A first contact is formed contacting the first spacers in the first cavity. A second contact is formed contacting the second spacers in the second cavity.

公开(公告)号：US10242982B2

公开(公告)日：2019-03-26

申请号：US15455313

申请日：2017-03-10

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Katsunori Onishi ,  Tek Po Rinus Lee

IPC: H01L27/088 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/311 ,  H01L29/423

Abstract: A method includes forming a first plurality of gate structures. A second plurality of gate structures is formed. A first spacer is formed on each of the first and second pluralities of gate structures. A first cavity is defined between the first spacers of a first pair of the first plurality of gate structures. A second cavity is defined between the first spacers of a second pair of the second plurality of gate structures. A second spacer is selectively formed in the second cavity on the first spacer of each of the gate structures of the second pair without forming the second spacer in the first cavity. A first contact is formed contacting the first spacers in the first cavity. A second contact is formed contacting the second spacers in the second cavity.

公开(公告)号：US10741668B2

公开(公告)日：2020-08-11

申请号：US15654234

申请日：2017-07-19

Applicant: GLOBALFOUNDRIES INC.

Inventor： Bala Haran ,  Ruilong Xie ,  Balaji Kannan ,  Katsunori Onishi ,  Vimal K. Kamineni

IPC: H01L29/66 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/161 ,  H01L21/285 ,  H01L29/78 ,  H01L27/092

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to replacement metal gate structures and methods of manufacture. The structure includes at least one short channel device including a dielectric material, a workfunction metal, and a capping material, and a long channel device comprising the dielectric material, the workfunction metal and fluorine free gate conductor material.

公开(公告)号：US10446550B2

公开(公告)日：2019-10-15

申请号：US15783549

申请日：2017-10-13

Applicant: GLOBALFOUNDRIES INC.

Inventor： Balaji Kannan ,  Ayse M. Ozbek ,  Tao Chu ,  Bala Haran ,  Vishal Chhabra ,  Katsunori Onishi ,  Guowei Xu

IPC: H01L27/092 ,  H01L29/06 ,  H01L27/02 ,  H01L21/311 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/027 ,  H01L21/8238 ,  H01L29/51 ,  H01L27/11

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a cut inside a replacement metal gate trench to mitigate n-p proximity effects and methods of manufacture. The structure described herein includes: a first device; a second device, adjacent to the first device; a dielectric material, of the first device and the second device, including a cut within a trench between the first device and the second device; and a common gate electrode shared with the first device and the second device, the common gate electrode provided over the dielectric material and contacting underlying material within the cut.

公开(公告)号：US10354928B2

公开(公告)日：2019-07-16

申请号：US16038977

申请日：2018-07-18

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Suraj Kumar Patil ,  Katsunori Onishi ,  Pei Liu ,  Chih-Chiang Chang

IPC: H01L21/82 ,  H01L21/8238 ,  H01L21/28 ,  H01L27/092 ,  H01L29/49

Abstract: A method of controlling NFET and PFET gate heights across different gate widths with chamfering and the resulting device are provided. Embodiments include forming an ILD over a fin; forming cavities in the ILD, each with similar or different widths; forming a high-K dielectric layer over the ILD and in each cavity; forming a pWF metal layer over the dielectric layer in one cavity; recessing the pWF metal layer to a height above the fin; forming an nWF metal layer in the cavities over the dielectric and pWF metal layers; recessing the nWF metal layer to a height above the pWF metal layer; forming a barrier layer over the dielectric and nWF metal layers; filling the cavities with a low-resistive metal; and recessing the barrier and dielectric layers to a height above the nWF metal layer; and concurrently etching the low-resistive metal.

公开(公告)号：US20190131424A1

公开(公告)日：2019-05-02

申请号：US15801722

申请日：2017-11-02

Applicant: GLOBALFOUNDRIES INC.

Inventor： Guowei Xu ,  Suraj K. Patil ,  Hui Zang ,  Katsunori Onishi ,  Keith H. Tabakman

IPC: H01L29/66 ,  H01L29/417 ,  H01L29/78

Abstract: The present disclosure relates to methods for forming IC structures having recessed gate spacers and related IC structures. A method may include: forming a first and second dummy gate over a fin, each dummy gate having gate spacers disposed on sidewalls thereof such that an opening is disposed between a first gate spacer and a second gate spacer, the opening exposing a source/drain region; recessing the first and second gate spacers; forming an etch stop layer within the opening such that the etch stop layer extends vertically along the recessed first and second gate spacers; forming a dielectric fill over the etch stop layer to substantially fill the opening; replacing the first and second dummy gates with first and second RMG structures; recessing the first and second RMG structures; and forming a gate cap layer over the first and second RMG structures.

公开(公告)号：US20190096679A1

公开(公告)日：2019-03-28

申请号：US15712996

申请日：2017-09-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Balaji Kannan ,  Bala Haran ,  Vimal K. Kamineni ,  Sungkee Han ,  Neal Makela ,  Suraj K. Patil ,  Pei Liu ,  Chih-Chiang Chang ,  Katsunori Onishi ,  Keith Kwong Hon Wong ,  Ruilong Xie ,  Chanro Park ,  Min Gyu Sung

IPC: H01L21/28 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78

Abstract: Structures for a field-effect transistor and methods for forming a structure for a field-effect transistor. A gate cavity is formed in a dielectric layer that includes a bottom surface and a plurality sidewalls that extend to the bottom surface. A gate dielectric layer is formed at the sidewalls and the bottom surface of the gate cavity. A work function metal layer is deposited on the gate dielectric layer at the sidewalls and the bottom surface of the gate cavity. A fill metal layer is deposited inside the gate cavity after the work function metal layer is deposited. The fill metal layer is formed in direct contact with the work function metal layer.

公开(公告)号：US10056303B1

公开(公告)日：2018-08-21

申请号：US15494119

申请日：2017-04-21

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Suraj Kumar Patil ,  Katsunori Onishi ,  Pei Liu ,  Chih-Chiang Chang

IPC: H01L21/82 ,  H01L21/8238 ,  H01L21/28 ,  H01L27/092 ,  H01L29/49

CPC classification number: H01L21/823842 ,  H01L21/28088 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/4966

Abstract: A method of controlling NFET and PFET gate heights across different gate widths with chamfering and the resulting device are provided. Embodiments include forming an ILD over a fin; forming cavities in the ILD, each with similar or different widths; forming a high-K dielectric layer over the ILD and in each cavity; forming a pWF metal layer over the dielectric layer in one cavity; recessing the pWF metal layer to a height above the fin; forming an nWF metal layer in the cavities over the dielectric and pWF metal layers; recessing the nWF metal layer to a height above the pWF metal layer; forming a barrier layer over the dielectric and nWF metal layers; filling the cavities with a low-resistive metal; and recessing the barrier and dielectric layers to a height above the nWF metal layer; and concurrently etching the low-resistive metal.

公开(公告)号：US20170338325A1

公开(公告)日：2017-11-23

申请号：US15160845

申请日：2016-05-20

Applicant: GLOBALFOUNDRIES INC.

Inventor： Huy Cao ,  Chih-Chiang Chang ,  Katsunori Onishi ,  Songkram Srivathanakul

IPC: H01L29/66 ,  H01L21/3105 ,  H01L21/02 ,  H01L27/088 ,  H01L21/8234

CPC classification number: H01L29/66545 ,  H01L21/0217 ,  H01L21/02274 ,  H01L21/02348 ,  H01L21/31055 ,  H01L21/823418 ,  H01L21/823437 ,  H01L27/088 ,  H01L29/78

Abstract: We disclose a semiconductor device, comprising a semiconductor substrate; at least one gate structure disposed above the semiconductor substrate, wherein the gate structure comprises a gate structure cavity partially filled with at least one metal layer; and an ultraviolet (UV) cured high density plasma (HDP) nitride cap layer in the gate structure cavity above the at least one metal layer. We also disclose at least one method and at least one system by which the semiconductor device may be formed. The UV cured HDP nitride cap layer may be substantially free of voids or seams, and as a result, the semiconductor device may have a reduced Vt shift relative to comparable semiconductor devices known in the art.