公开(公告)号：US10032870B2

公开(公告)日：2018-07-24

申请号：US14645449

申请日：2015-03-12

Applicant: GLOBALFOUNDRIES INC.

Inventor： Joel P. de Souza ,  Keith E. Fogel ,  Alexander Reznicek ,  Dominic J. Schepis

IPC: H01L29/20 ,  H01L29/16 ,  H01L21/02 ,  H01L29/36

Abstract: A method of forming a semiconductor on a porous semiconductor structure. The method may include forming a stack, the stack includes (from bottom to top) a substrate, a base silicon layer, a thick silicon layer, and a thin silicon layer, where the thin silicon layer and the thick silicon layer are relaxed; converting the thick silicon layer into a porous silicon layer using a porousification process; and forming a III-V layer on the thin silicon layer, where the III-V layer is relaxed, the thin silicon layer is strained, and the porous silicon layer is partially strained.

公开(公告)号：US09666674B2

公开(公告)日：2017-05-30

申请号：US14691270

申请日：2015-04-20

Applicant: GLOBALFOUNDRIES INC.

Inventor： Christos D. Dimitrakopoulos ,  Keith E. Fogel ,  Jeehwan Kim ,  Hongsik Park

IPC: H01L29/06 ,  H01L29/16 ,  H01L21/027 ,  H01L21/20 ,  B32B9/04 ,  B32B37/26 ,  B32B38/10 ,  C01B31/00 ,  C01B31/04 ,  B32B9/00 ,  H01L23/532

CPC classification number: H01L29/1606 ,  B32B9/007 ,  B32B9/041 ,  B32B38/10 ,  B32B2307/202 ,  B32B2307/704 ,  C01B32/188 ,  H01L21/0272 ,  H01L21/2007 ,  H01L23/53276 ,  H01L2924/0002 ,  Y10T156/11 ,  Y10T156/1153 ,  Y10T428/24612 ,  Y10T428/26 ,  H01L2924/00

Abstract: A method for transfer of a two-dimensional material includes forming a spreading layer of a two-dimensional material on a first substrate. The spreading layer has at least one monolayer. A stressor layer is formed on the spreading layer. The stressor layer is configured to apply stress to a closest monolayer of the spreading layer. The closest monolayer is exfoliated by mechanically splitting the spreading layer wherein at least the closest monolayer remains on the stressor layer. The at least one monolayer is stamped against a second substrate to adhere remnants of the two-dimensional material on the at least one monolayer to the second substrate to provide a single monolayer on the stressor layer. The single monolayer is transferred to a third substrate.

公开(公告)号：US09716207B2

公开(公告)日：2017-07-25

申请号：US13948645

申请日：2013-07-23

Applicant: GLOBALFOUNDRIES INC.

Inventor： Keith E. Fogel ,  Jeehwan Kim ,  David B. Mitzi ,  Mark T. Winkler

IPC: H01L21/00 ,  H01L31/18 ,  H01L31/0224 ,  H01L31/0236 ,  H01L31/032 ,  H01L31/0749

CPC classification number: H01L31/1888 ,  H01L31/022483 ,  H01L31/02366 ,  H01L31/0326 ,  H01L31/0749 ,  Y02E10/541

Abstract: A method for forming a photovoltaic device includes forming a photovoltaic absorption stack on a substrate including one or more of I-III-VI2 and I2-II-IV-VI4 semiconductor material. A transparent conductive contact layer is deposited on the photovoltaic absorption stack at a temperature less than 200 degrees Celsius. The transparent conductive contact layer has a thickness of about one micron and is formed on a front light-receiving surface. The surface includes pyramidal structures due to an as deposited thickness. The transparent conductive contact layer is wet etched to further roughen the front light-receiving surface to reduce reflectance.

公开(公告)号：US20160268123A1

公开(公告)日：2016-09-15

申请号：US14645449

申请日：2015-03-12

Applicant: GLOBALFOUNDRIES INC.

Inventor： Joel P. de Souza ,  Keith E. Fogel ,  Alexander Reznicek ,  Dominic J. Schepis

IPC: H01L21/02 ,  H01L29/16 ,  H01L29/207 ,  H01L29/10 ,  H01L29/36

CPC classification number: H01L29/16 ,  H01L21/0245 ,  H01L21/02505 ,  H01L21/02513 ,  H01L21/02538 ,  H01L21/02658 ,  H01L29/36

Abstract: A method of forming a semiconductor on a porous semiconductor structure. The method may include forming a stack, the stack includes (from bottom to top) a substrate, a base silicon layer, a thick silicon layer, and a thin silicon layer, where the thin silicon layer and the thick silicon layer are relaxed; converting the thick silicon layer into a porous silicon layer using a porousification process; and forming a III-V layer on the thin silicon layer, where the III-V layer is relaxed, the thin silicon layer is strained, and the porous silicon layer is partially strained.

Abstract translation: 一种在多孔半导体结构上形成半导体的方法。 该方法可以包括形成堆叠，堆叠包括（从底部到顶部）衬底，基底硅层，厚硅层和薄硅层，其中薄硅层和厚硅层被松弛; 使用多孔化方法将厚硅层转化为多孔硅层; 在薄硅层上形成III-V层，III-V层被松弛，薄硅层变形，多孔硅层部分变形。

公开(公告)号：US09337274B2

公开(公告)日：2016-05-10

申请号：US13894954

申请日：2013-05-15

Applicant: GLOBALFOUNDRIES INC.

Inventor： Christos D. Dimitrakopoulos ,  Keith E. Fogel ,  Jeehwan Kim ,  Hongsik Park

IPC: H01L29/06 ,  H01L21/027 ,  H01L21/20 ,  B32B37/14 ,  C01B31/00 ,  B32B38/10 ,  B32B9/04 ,  H01L29/16 ,  B32B37/26 ,  C01B31/04 ,  B32B9/00 ,  H01L23/532

CPC classification number: H01L29/1606 ,  B32B9/007 ,  B32B9/041 ,  B32B38/10 ,  B32B2307/202 ,  B32B2307/704 ,  C01B32/188 ,  H01L21/0272 ,  H01L21/2007 ,  H01L23/53276 ,  H01L2924/0002 ,  Y10T156/11 ,  Y10T156/1153 ,  Y10T428/24612 ,  Y10T428/26 ,  H01L2924/00

Abstract: A method for transfer of a two-dimensional material includes forming a spreading layer of a two-dimensional material on a first substrate. The spreading layer has at least one monolayer. A stressor layer is formed on the spreading layer. The stressor layer is configured to apply stress to a closest monolayer of the spreading layer. The closest monolayer is exfoliated by mechanically splitting the spreading layer wherein at least the closest monolayer remains on the stressor layer. The at least one monolayer is stamped against a second substrate to adhere remnants of the two-dimensional material on the at least one monolayer to the second substrate to provide a single monolayer on the stressor layer. The single monolayer is transferred to a third substrate.

公开(公告)号：US20190043956A1

公开(公告)日：2019-02-07

申请号：US16018304

申请日：2018-06-26

Applicant: GLOBALFOUNDRIES INC.

Inventor： Joel P. de Souza ,  Keith E. Fogel ,  Alexander Reznicek ,  Dominic J. Schepis

IPC: H01L29/16 ,  H01L21/02

Abstract: A method of forming a semiconductor on a porous semiconductor structure. The method may include forming a stack, the stack includes (from bottom to top) a substrate, a base silicon layer, a thick silicon layer, and a thin silicon layer, where the thin silicon layer and the thick silicon layer are relaxed; converting the thick silicon layer into a porous silicon layer using a porousification process; and forming a III-V layer on the thin silicon layer, where the layer is relaxed, the thin silicon layer is strained, and the porous silicon layer is partially strained.

公开(公告)号：US09574287B2

公开(公告)日：2017-02-21

申请号：US14038139

申请日：2013-09-26

Applicant: GLOBALFOUNDRIES INC.

Inventor： Can Bayram ,  Christos D. Dimitrakopoulos ,  Keith E. Fogel ,  Jeehwan Kim ,  John A. Ott ,  Devendra K. Sadana

IPC: C30B25/00 ,  C30B25/18 ,  C30B29/40 ,  H01L21/02 ,  H01L29/16 ,  H01L33/00 ,  H01L33/32 ,  C30B29/02 ,  H01L33/12

CPC classification number: C30B25/18 ,  C30B25/183 ,  C30B29/02 ,  C30B29/406 ,  H01L21/0254 ,  H01L29/1606 ,  H01L33/0025 ,  H01L33/0079 ,  H01L33/12 ,  H01L33/32

Abstract: A method of forming an epitaxial semiconductor material that includes forming a graphene layer on a semiconductor and carbon containing substrate and depositing a metal containing monolayer on the graphene layer. An epitaxial layer of a gallium containing material is formed on the metal containing monolayer. A layered stack of the metal containing monolayer and the epitaxial layer of gallium containing material is cleaved from the graphene layer that is present on the semiconductor and carbon containing substrate.

Abstract translation: 一种形成外延半导体材料的方法，其包括在半导体和含碳衬底上形成石墨烯层并在所述石墨烯层上沉积含金属的单层。 在含金属单层上形成含镓材料的外延层。 含有金属的单层的层叠堆叠和含镓材料的外延层从存在于半导体和含碳衬底上的石墨烯层切割。

公开(公告)号：US20160343623A1

公开(公告)日：2016-11-24

申请号：US14718760

申请日：2015-05-21

Applicant: GLOBALFOUNDRIES INC.

Inventor： Keith E. Fogel ,  Alexander Reznicek ,  Devendra K. Sadana ,  Dominic J. Schepis

IPC: H01L21/8238 ,  H01L29/10 ,  H01L27/092

CPC classification number: H01L21/823878 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823892 ,  H01L27/0924 ,  H01L29/1083 ,  H01L29/66803 ,  H01L29/785

Abstract: A punch through stop layer is formed in a bulk FinFET structure using doped oxides. Dopants are driven into the substrate and base portions of the fins by annealing. The punch through stop layer includes a p-type region and an n-type region, both of which may extend substantially equal distances into the semiconductor fins.

Abstract translation: 通过使用掺杂氧化物的体积FinFET结构形成穿通停止层。 通过退火将掺杂剂驱入散热片的基板和基部。 穿通停止层包括p型区域和n型区域，它们都可以延伸到半导体鳍片中基本相等的距离。

公开(公告)号：US20160190302A1

公开(公告)日：2016-06-30

申请号：US14585742

申请日：2014-12-30

Applicant: GLOBALFOUNDRIES INC.

Inventor： Stephen W. Bedell ,  Joel P. de Souza ,  Keith E. Fogel ,  Alexander Reznicek ,  Devendra K. Sadana ,  Dominic J. Schepis

IPC: H01L29/78 ,  H01L29/161 ,  H01L29/06 ,  H01L29/167 ,  H01L21/84 ,  H01L21/02 ,  H01L21/322 ,  H01L21/324 ,  H01L29/66 ,  H01L21/762

CPC classification number: H01L29/785 ,  H01L21/02164 ,  H01L21/02238 ,  H01L21/7624 ,  H01L21/845 ,  H01L29/0649 ,  H01L29/161 ,  H01L29/167 ,  H01L29/66795 ,  H01L29/7848

Abstract: A method of fabricating a semiconductor device where: (i) the fins are formed over a porous semiconductor material layer (for example, a silicon layer); and (ii) the porous semiconductor layer is then oxidized to form an insulator layer (for example, a SiO2 buried oxide layer). The pores in the porous semiconductor layer facilitate reliable oxidation of the insulator layer by allowing penetration of gaseous oxygen (O2) throughout the layer as it is oxidized to form the insulator layer. In some of these embodiments, a thin non-porous semiconductor layer is located over the porous semiconductor layer (prior to its oxidation) to allow strained epitaxial growth of material to be used in making source regions and drain regions of the finished semiconductor device (for example, a FINFET).

Abstract translation: 一种制造半导体器件的方法，其中：（i）所述散热片形成在多孔半导体材料层（例如，硅层）上; 和（ii）然后氧化多孔半导体层以形成绝缘体层（例如，SiO 2掩埋氧化物层）。 多孔半导体层中的孔促进了绝缘体层的可靠氧化，允许气态氧（O 2）在整个层中被氧化以形成绝缘体层。 在这些实施例的一些中，薄的无孔半导体层位于多孔半导体层之上（在其氧化之前），以允许材料的应变外延生长用于制造成品半导体器件的源极区域和漏极区域（用于 例如，FINFET）。

公开(公告)号：US09601624B2

公开(公告)日：2017-03-21

申请号：US14585742

申请日：2014-12-30

Applicant: GLOBALFOUNDRIES INC.

Inventor： Stephen W. Bedell ,  Joel P. de Souza ,  Keith E. Fogel ,  Alexander Reznicek ,  Devendra K. Sadana ,  Dominic J. Schepis

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/161 ,  H01L29/06 ,  H01L21/84 ,  H01L21/02 ,  H01L29/167 ,  H01L21/762

CPC classification number: H01L29/785 ,  H01L21/02164 ,  H01L21/02238 ,  H01L21/7624 ,  H01L21/845 ,  H01L29/0649 ,  H01L29/161 ,  H01L29/167 ,  H01L29/66795 ,  H01L29/7848

Abstract: A method of fabricating a semiconductor device where: (i) the fins are formed over a porous semiconductor material layer (for example, a silicon layer); and (ii) the porous semiconductor layer is then oxidized to form an insulator layer (for example, a SiO2 buried oxide layer). The pores in the porous semiconductor layer facilitate reliable oxidation of the insulator layer by allowing penetration of gaseous oxygen (O2) throughout the layer as it is oxidized to form the insulator layer. In some of these embodiments, a thin non-porous semiconductor layer is located over the porous semiconductor layer (prior to its oxidation) to allow strained epitaxial growth of material to be used in making source regions and drain regions of the finished semiconductor device (for example, a FINFET).