公开(公告)号：US10217852B1

公开(公告)日：2019-02-26

申请号：US15948486

申请日：2018-04-09

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Qizhi Liu ,  Vibhor Jain ,  James W. Adkisson ,  James R. Elliott

IPC: H01L23/552 ,  H01L29/737 ,  H01L29/10 ,  H01L21/306 ,  H01L29/06 ,  H01L29/66 ,  H01L29/04

Abstract: Device structures and fabrication methods for heterojunction bipolar transistors. A trench isolation region surrounds an active region that includes a collector, and a base layer includes a first section composed of a single-crystal semiconductor material that is arranged over the active region and a second section composed of polycrystalline semiconductor material that is arranged over the trench isolation region. A first semiconductor layer of the second section of the base layer is removed selective to a second semiconductor layer of the second section of the base layer to define a gap arranged in a vertical direction between the second semiconductor layer of the second section of the base layer and the trench isolation region. An emitter is formed on the first section of the base layer.

公开(公告)号：US10163955B2

公开(公告)日：2018-12-25

申请号：US15671223

申请日：2017-08-08

Applicant: GLOBALFOUNDRIES INC.

Inventor： John J. Ellis-Monaghan ,  Qizhi Liu ,  Steven M. Shank

IPC: H01L27/146 ,  H01L31/101 ,  G02B6/42 ,  H01L31/0232 ,  H01L21/762

Abstract: Disclosed are structures and methods of forming the structures so as to have a photodetector isolated from a substrate by stacked trench isolation regions. In one structure, a first trench isolation region is in and at the top surface of a substrate and a second trench isolation region is in the substrate below the first. A photodetector is on the substrate aligned above the first and second trench isolation regions. In another structure, a semiconductor layer is on an insulator layer and laterally surrounded by a first trench isolation region. A second trench isolation region is in and at the top surface of a substrate below the insulator layer and first trench isolation region. A photodetector is on the semiconductor layer and extends laterally onto the first trench isolation region. The stacked trench isolation regions provide sufficient isolation below the photodetector to allow for direct coupling with an off-chip optical fiber.

公开(公告)号：US10134880B2

公开(公告)日：2018-11-20

申请号：US15473043

申请日：2017-03-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Vibhor Jain ,  Qizhi Liu ,  Alvin J. Joseph ,  Pernell Dongmo

IPC: H01L21/331 ,  H01L29/732 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/66 ,  H01L21/311 ,  H01L21/02 ,  H01L29/737 ,  H01L29/165

Abstract: Fabrication methods and device structures for bipolar junction transistors and heterojunction bipolar transistors. A first dielectric layer is formed and a second dielectric layer is formed on the first dielectric layer. An opening is etched extending vertically through the first dielectric layer and the second dielectric layer. A collector is formed inside the opening. An intrinsic base, which is also formed inside the opening, has a vertical arrangement relative to the collector.

公开(公告)号：US20180069106A1

公开(公告)日：2018-03-08

申请号：US15806532

申请日：2017-11-08

Applicant: GLOBALFOUNDRIES INC.

Inventor： Vibhor Jain ,  Qizhi Liu

IPC: H01L29/737 ,  H01L21/8228 ,  H01L27/082 ,  H01L21/8226 ,  H03F3/213 ,  H01L29/66 ,  H01L29/04 ,  H01L29/165 ,  H01L29/161 ,  H01L21/8222

CPC classification number: H01L29/7378 ,  H01L21/8222 ,  H01L21/8226 ,  H01L21/82285 ,  H01L21/8249 ,  H01L27/0623 ,  H01L27/0823 ,  H01L27/0825 ,  H01L27/0826 ,  H01L29/04 ,  H01L29/0817 ,  H01L29/0821 ,  H01L29/0826 ,  H01L29/1004 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66242 ,  H01L29/66272 ,  H01L29/66287 ,  H01L29/7322 ,  H01L29/7371 ,  H03F3/213 ,  H03F2200/294

Abstract: Methods according to the present disclosure include: providing a substrate including: a first semiconductor region, a second semiconductor region, and a trench isolation (TI) laterally between the first and second semiconductor regions; forming an epitaxial layer on at least the first semiconductor region of the substrate, wherein the epitaxial layer includes a first semiconductor base material positioned above the first semiconductor region of the substrate; forming an insulator region on at least the first semiconductor base material, the trench isolation (TI), and the second semiconductor region; forming a first opening in the insulator over the second semiconductor region; and growing a second semiconductor base material in the first opening, wherein a height of the second semiconductor base material above the substrate is greater than a height of the first semiconductor base material above the substrate.

公开(公告)号：US20170358619A1

公开(公告)日：2017-12-14

申请号：US15671223

申请日：2017-08-08

Applicant: GLOBALFOUNDRIES INC.

Inventor： John J. Ellis-Monaghan ,  Qizhi Liu ,  Steven M. Shank

IPC: H01L27/146 ,  H01L31/0232 ,  H01L21/762

CPC classification number: H01L27/14632 ,  G02B6/4202 ,  H01L21/76224 ,  H01L21/76283 ,  H01L27/1462 ,  H01L27/1463 ,  H01L27/14685 ,  H01L27/14687 ,  H01L31/0232 ,  H01L31/02327 ,  H01L31/101

Abstract: Disclosed are structures and methods of forming the structures so as to have a photodetector isolated from a substrate by stacked trench isolation regions. In one structure, a first trench isolation region is in and at the top surface of a substrate and a second trench isolation region is in the substrate below the first. A photodetector is on the substrate aligned above the first and second trench isolation regions. In another structure, a semiconductor layer is on an insulator layer and laterally surrounded by a first trench isolation region. A second trench isolation region is in and at the top surface of a substrate below the insulator layer and first trench isolation region. A photodetector is on the semiconductor layer and extends laterally onto the first trench isolation region. The stacked trench isolation regions provide sufficient isolation below the photodetector to allow for direct coupling with an off-chip optical fiber.

公开(公告)号：US20170278955A1

公开(公告)日：2017-09-28

申请号：US15081443

申请日：2016-03-25

Applicant: GLOBALFOUNDRIES INC.

Inventor： Vibhor Jain ,  Renata Camillo-Castillo ,  Qizhi Liu ,  John J. Pekarik ,  Alvin J. Joseph ,  Peter B. Gray

IPC: H01L29/732 ,  H01L21/762 ,  H01L29/08 ,  H01L29/417 ,  H01L29/06 ,  H01L29/10

CPC classification number: H01L29/732 ,  H01L21/76224 ,  H01L29/0649 ,  H01L29/0804 ,  H01L29/0821 ,  H01L29/1004 ,  H01L29/41708 ,  H01L29/73

Abstract: Device structures for a bipolar junction transistor and methods for fabricating a device structure using a substrate. One or more primary trench isolation regions are formed that surround an active device region of the substrate and a collector contact region of the substrate. A base layer is formed on the active device region and the collector contact region, and the active device region includes a collector. Each primary trench isolation region extends vertically to a first depth into the substrate. A trench is formed laterally located between the base layer and the collector contact region and that extends vertically through the base layer and into the substrate to a second depth that is less than the first depth. A dielectric is formed in the trench to form a secondary trench isolation region. An emitter is formed on the base layer.

公开(公告)号：US09590082B1

公开(公告)日：2017-03-07

申请号：US14965267

申请日：2015-12-10

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Vibhor Jain ,  Qizhi Liu

IPC: H01L29/08 ,  H01L29/737 ,  H01L29/165 ,  H01L29/66 ,  H01L29/06 ,  H01L29/10

CPC classification number: H01L29/737 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/1004 ,  H01L29/1008 ,  H01L29/165 ,  H01L29/66242 ,  H01L29/7371

Abstract: Device structures and fabrication methods for a heterojunction bipolar transistor. A first base layer is formed on a first device region of a substrate. A first emitter is formed that defines a first junction with the first base layer. A second base layer is formed on a second device region of a substrate. A second emitter is formed that defines a second junction with the second base layer. The first base layer and the second base layer differ in thickness, composition, concentration of an electrically-active dopant, or a combination thereof.

Abstract translation: 异质结双极晶体管的器件结构和制造方法。 第一基层形成在基板的第一器件区域上。 形成第一发射极，其限定与第一基极层的第一结。 第二基层形成在基板的第二器件区域上。 形成第二发射极，其限定与第二基极层的第二结。 第一基底层和第二基底层的厚度，组成，电活性掺杂剂的浓度或其组合不同。

公开(公告)号：US20160379930A1

公开(公告)日：2016-12-29

申请号：US14746891

申请日：2015-06-23

Applicant: GLOBALFOUNDRIES INC.

Inventor： Vibhor Jain ,  Qizhi Liu ,  Ian A. McCallum-Cook

IPC: H01L23/525

CPC classification number: H01L23/5256 ,  H01L21/7682 ,  H01L23/522 ,  H01L23/5329

Abstract: Electrical fuses and methods for forming an electrical fuse. A semiconductor substrate is implanted to define a modified region in the semiconductor substrate. Trenches that surround the modified region and that penetrate into the semiconductor substrate to a depth greater than a depth of the modified region are formed in the modified region so as to define a fuse link of the electrical fuse. The substrate is removed from beneath the fuse link with a selective etching process that removes the semiconductor substrate with a first etch rate that is higher than a second etch rate of the modified region.

Abstract translation: 电熔丝和形成电熔丝的方法。 植入半导体衬底以限定半导体衬底中的改性区域。 围绕改性区域并且穿透到半导体衬底中的深度大于修饰区域的深度的沟槽形成在修改区域中，以便限定电熔丝的熔断体。 通过选择性蚀刻工艺从熔丝链下方去除衬底，其以比修改区域的第二蚀刻速率高的第一蚀刻速率去除半导体衬底。

公开(公告)号：US09385022B2

公开(公告)日：2016-07-05

申请号：US14283984

申请日：2014-05-21

Applicant: GLOBALFOUNDRIES INC.

Inventor： Mark D. Jaffe ,  Alvin J. Joseph ,  Qizhi Liu ,  Anthony K. Stamper

IPC: H01L21/76 ,  H01L21/762 ,  H01L29/06 ,  G02B6/134 ,  G02B6/136 ,  G02B6/132 ,  G02B6/12 ,  G02B6/122

CPC classification number: H01L21/76224 ,  G02B6/12004 ,  G02B6/122 ,  G02B6/132 ,  G02B6/1347 ,  G02B6/136 ,  G02B2006/12061 ,  H01L21/762 ,  H01L29/06 ,  H01L29/0649

Abstract: Various methods include: forming an optical waveguide in a bulk silicon layer, the optical waveguide including a set of shallow trench isolation (STI) regions overlying a silicon substrate region; ion implanting the silicon substrate to amorphize a portion of the silicon substrate; forming a set of trenches through the STI regions and into the underlying silicon substrate region; undercut etching the silicon substrate region under the STI regions through the set of trenches to form a set of cavities, wherein the at least partially amorphized portion of the silicon substrate etches at a rate less than an etch rate of the silicon substrate; and sealing the set of cavities.

Abstract translation: 各种方法包括：在体硅层中形成光波导，光波导包括覆盖硅衬底区域的一组浅沟槽隔离（STI）区域; 离子注入硅衬底以使硅衬底的一部分非晶化; 通过STI区域形成一组沟槽并进入下面的硅衬底区域; 底切蚀刻在STI区域下方的硅衬底区域通过该组沟槽以形成一组空穴，其中硅衬底的至少部分非晶化部分以小于硅衬底的蚀刻速率的速率蚀刻; 并密封该组腔。

公开(公告)号：US20160170140A1

公开(公告)日：2016-06-16

申请号：US15041103

申请日：2016-02-11

Applicant: GLOBALFOUNDRIES INC.

Inventor： Zhong-Xiang He ,  Qizhi Liu ,  Ronald G. Meunier ,  Steven M. Shank

IPC: G02B6/12 ,  G02B6/132 ,  G02B6/122 ,  G02B6/136

CPC classification number: G02B6/12002 ,  G02B6/122 ,  G02B6/132 ,  G02B6/136 ,  G02B6/42 ,  G02B2006/121 ,  G02B2006/12119

Abstract: Disclosed are structures with an optical waveguide having a first segment at a first level and a second segment extending between the first level and a higher second level and further extending along the second level. Specifically, the waveguide comprises a first segment between first and second dielectric layers. The second dielectric layer has a trench, which extends through to the first dielectric layer and which has one side positioned laterally adjacent to an end of the first segment. The waveguide also comprises a second segment extending from the bottom of the trench on the side adjacent to the first segment up to and along the top surface of the second dielectric layer on the opposite side of the trench. A third dielectric layer covers the second segment in the trench and on the top surface of the second dielectric layer. Also disclosed are methods of forming such optoelectronic structures.