公开(公告)号：US10411010B2

公开(公告)日：2019-09-10

申请号：US15862064

申请日：2018-01-04

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ruilong Xie ,  Andreas Knorr ,  Murat Kerem Akarvardar ,  Lars Liebmann ,  Nigel Graeme Cave

IPC: H01L27/088 ,  H01L29/45 ,  H01L29/423 ,  H01L21/8234 ,  H01L29/66 ,  H01L21/8238 ,  H01L29/78 ,  H01L27/092

Abstract: Disclosed are methods of forming improved fin-type field effect transistor (FINFET) structures and, particularly, relatively tall single-fin FINFET structures that provide increased drive current over conventional single-fin FINFET structures. The use of such a tall single-fin FINFET provides significant area savings over a FINFET that requires multiple semiconductor fins to achieve the same amount of drive current. Furthermore, since only a single fin is used, only a single leakage path is present at the bottom of the device. Thus, the disclosed FINFET structures can be incorporated into a cell in place of multi-fin FINFETs in order to allow for cell height scaling without violating critical design rules or sacrificing performance.

公开(公告)号：US20190214482A1

公开(公告)日：2019-07-11

申请号：US15865973

申请日：2018-01-09

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ruilong Xie ,  Julien Frougier ,  Yi Qi ,  Nigel G. Cave ,  Edward J. Nowak ,  Andreas Knorr

IPC: H01L29/66 ,  H01L29/161 ,  H01L21/02 ,  H01L29/10 ,  H01L29/06 ,  H01L21/308 ,  H01L29/78

CPC classification number: H01L29/66598 ,  H01L21/02532 ,  H01L21/3086 ,  H01L27/00 ,  H01L29/0673 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/66545 ,  H01L29/66818 ,  H01L2029/7858

Abstract: A semiconductor structure including a first substantially U-shaped and/or H-shaped channel is disclosed. The semiconductor structure may further include a second substantially U-shaped and/or H-shaped channel positioned above the first channel. A method of forming a substantially U-shaped and/or H-shaped channel is also disclosed. The method may include forming a fin structure on a substrate where the fin structure includes an alternating layers of sacrificial semiconductor and at least one silicon layer or region. The method may further include forming additional silicon regions vertically on sidewalls of the fin structure. The additional silicon regions may contact the silicon layer or region of the fin structure to form the substantially U-shaped and/or H-shaped channel(s). The method may further include removing the sacrificial semiconductor layers and forming a gate structure around the substantially U-shaped and/or substantially H-shaped channels.

公开(公告)号：US20190074224A1

公开(公告)日：2019-03-07

申请号：US15695229

申请日：2017-09-05

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ruilong Xie ,  Julien Frougier ,  Min Gyu Sung ,  Edward Joseph Nowak ,  Nigel G. Cave ,  Lars Liebmann ,  Daniel Chanemougame ,  Andreas Knorr

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L29/66

Abstract: The disclosure is directed to gate all-around integrated circuit structures, finFETs having a dielectric isolation, and methods of forming the same. The gate all-around integrated circuit structure may include a first insulator region within a substrate; a pair of remnant liner stubs disposed within the first insulator region; a second insulator region laterally adjacent to the first insulator region within the substrate; a pair of fins over the first insulator region, each fin in the pair of fins including an inner sidewall facing the inner sidewall of an adjacent fin in the pair of fins and an outer sidewall opposite the inner sidewall; and a gate structure substantially surrounding an axial portion of the pair of fins and at least partially disposed over the first and second insulator regions, wherein each remnant liner stub is substantially aligned with the inner sidewall of a respective fin of the pair of fins.

公开(公告)号：US09780178B2

公开(公告)日：2017-10-03

申请号：US14731960

申请日：2015-06-05

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Andre Labonte ,  Andreas Knorr

IPC: H01L21/00 ,  H01L29/423 ,  H01L23/535 ,  H01L29/06 ,  H01L29/78 ,  H01L21/28

CPC classification number: H01L29/4232 ,  H01L21/28008 ,  H01L23/535 ,  H01L29/0649 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

Abstract: One method disclosed herein includes, among other things, forming a gate contact opening in a layer of insulating material, wherein the gate contact opening is positioned at least partially vertically above a active region, the gate contact opening exposing a portion of at least a gate cap layer of a gate structure, performing at least one etching process to remove the gate cap layer and recess a sidewall spacer so as to thereby define a spacer cavity and expose at least an upper surface of a gate electrode within the gate contact opening, filling the spacer cavity with an insulating material while leaving the upper surface of the gate electrode exposed, and forming a conductive gate contact in the gate contact opening.

公开(公告)号：US09147748B1

公开(公告)日：2015-09-29

申请号：US14267555

申请日：2014-05-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Xiuyu Cai ,  Ajey Poovannummoottil Jacob ,  Andreas Knorr ,  Christopher Prindle

IPC: H01L21/283 ,  H01L29/66 ,  H01L21/311 ,  H01L21/285 ,  H01L29/45 ,  H01L29/51 ,  H01L29/49 ,  H01L29/06 ,  H01L29/78

CPC classification number: H01L29/41758 ,  H01L21/28518 ,  H01L21/31111 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76897 ,  H01L23/485 ,  H01L29/0642 ,  H01L29/0649 ,  H01L29/41775 ,  H01L29/41783 ,  H01L29/42372 ,  H01L29/45 ,  H01L29/456 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66659 ,  H01L29/78

Abstract: One illustrative method disclosed herein includes removing the sidewall spacers and a gate cap layer so as to thereby expose an upper surface and sidewalls of a sacrificial gate structure, forming an etch stop layer above source/drain regions of a device and on the sidewalls and upper surface of the sacrificial gate structure, forming a first layer of insulating material above the etch stop layer, removing the sacrificial gate structure so as to define a replacement gate cavity that is laterally defined by portions of the etch stop layer, forming a replacement gate structure in the replacement gate cavity, and forming a second gate cap layer above the replacement gate structure.

Abstract translation: 本文公开的一种示例性方法包括去除侧壁间隔件和栅极盖层，从而暴露牺牲栅极结构的上表面和侧壁，在器件的源极/漏极区域上方以及在侧壁和上部上形成蚀刻停止层 牺牲栅极结构的表面，在蚀刻停止层上方形成第一绝缘材料层，去除牺牲栅极结构，以便限定由蚀刻停止层的部分横向限定的替代栅极腔，形成替代栅极结构 并且在替换栅极结构上方形成第二栅极盖层。

公开(公告)号：US10381459B2

公开(公告)日：2019-08-13

申请号：US15865973

申请日：2018-01-09

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ruilong Xie ,  Julien Frougier ,  Yi Qi ,  Nigel G. Cave ,  Edward J. Nowak ,  Andreas Knorr

IPC: H01L21/44 ,  H01L29/66 ,  H01L29/10 ,  H01L21/02 ,  H01L21/308 ,  H01L29/161 ,  H01L29/06 ,  H01L29/78

Abstract: A semiconductor structure including a first substantially U-shaped and/or H-shaped channel is disclosed. The semiconductor structure may further include a second substantially U-shaped and/or H-shaped channel positioned above the first channel. A method of forming a substantially U-shaped and/or H-shaped channel is also disclosed. The method may include forming a fin structure on a substrate where the fin structure includes an alternating layers of sacrificial semiconductor and at least one silicon layer or region. The method may further include forming additional silicon regions vertically on sidewalls of the fin structure. The additional silicon regions may contact the silicon layer or region of the fin structure to form the substantially U-shaped and/or H-shaped channel(s). The method may further include removing the sacrificial semiconductor layers and forming a gate structure around the substantially U-shaped and/or substantially H-shaped channels.

公开(公告)号：US09691897B2

公开(公告)日：2017-06-27

申请号：US14867193

申请日：2015-09-28

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Andre Labonte ,  Andreas Knorr

IPC: H01L21/02 ,  H01L29/78 ,  H01L29/423 ,  H01L29/45 ,  H01L29/66

CPC classification number: H01L29/7845 ,  H01L21/76883 ,  H01L21/76895 ,  H01L21/76897 ,  H01L29/41791 ,  H01L29/42356 ,  H01L29/45 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785

Abstract: A three-dimensional transistor includes a semiconductor substrate, a fin coupled to the substrate, the fin including an active region across a top portion thereof, the active region including a source, a drain and a channel region therebetween. The transistor further includes a gate situated above the channel region, and a gate contact situated in the active region, no portion thereof being electrically coupled to the source or drain. The transistor is achieved by removing a portion of the source/drain contact situated beneath the gate contact during fabrication.

公开(公告)号：US09614056B2

公开(公告)日：2017-04-04

申请号：US14525288

申请日：2014-10-28

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Andreas Knorr

IPC: H01L29/76 ,  H01L29/66 ,  H01L29/78 ,  H01L27/12 ,  H01L21/84 ,  H01L21/8234 ,  H01L27/11 ,  H01L21/8238

CPC classification number: H01L29/6681 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/1104 ,  H01L27/1108 ,  H01L27/1211 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/6653 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/7841 ,  H01L29/785 ,  H01L29/7853

Abstract: One illustrative method disclosed herein includes, among other things, forming a fin that is positioned above and vertically spaced apart from an upper surface of a semiconductor substrate, the fin having an upper surface, a lower surface and first and second side surfaces, wherein an axis of the fin in a height direction of the fin is oriented substantially parallel to the upper surface of the substrate, and wherein a first side surface of the fin contacts a first insulating material, forming a gate structure around the upper surface, the second side surface and the lower surface of the fin, and forming a gate contact structure that is conductively coupled to the gate structure.

公开(公告)号：US20160359009A1

公开(公告)日：2016-12-08

申请号：US14731960

申请日：2015-06-05

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Andre Labonte ,  Andreas Knorr

IPC: H01L29/423 ,  H01L29/06 ,  H01L21/02 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/28 ,  H01L23/535 ,  H01L29/78

CPC classification number: H01L29/4232 ,  H01L21/28008 ,  H01L23/535 ,  H01L29/0649 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

Abstract: One method disclosed herein includes, among other things, forming a gate contact opening in a layer of insulating material, wherein the gate contact opening is positioned at least partially vertically above a active region, the gate contact opening exposing a portion of at least a gate cap layer of a gate structure, performing at least one etching process to remove the gate cap layer and recess a sidewall spacer so as to thereby define a spacer cavity and expose at least an upper surface of a gate electrode within the gate contact opening, filling the spacer cavity with an insulating material while leaving the upper surface of the gate electrode exposed, and forming a conductive gate contact in the gate contact opening.

Abstract translation: 本文公开的一种方法包括在绝缘材料层中形成栅极接触开口，其中栅极接触开口至少部分地垂直于有源区域上方，栅极接触开口暴露至少一个栅极的一部分 盖层，执行至少一个蚀刻工艺以去除栅极盖层并凹陷侧壁间隔件，从而限定间隔件空腔并暴露门接触开口内的至少栅极电极的上表面，填充 在离开栅电极的上表面的情况下，具有绝缘材料的间隔腔暴露，并且在栅极接触开口中形成导电栅极接触。

公开(公告)号：US09443976B1

公开(公告)日：2016-09-13

申请号：US14931409

申请日：2015-11-03

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Andreas Knorr

IPC: H01L29/66 ,  H01L29/78 ,  H01L27/088

CPC classification number: H01L29/7827 ,  H01L21/823431 ,  H01L21/823487 ,  H01L27/0886 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851 ,  H01L2029/7858

Abstract: One example of a novel integrated circuit product disclosed herein includes, among other things, a lateral FinFET device comprising a first gate structure having a first upper surface positioned above a semiconductor substrate and a vertical FinFET device comprising a second gate structure having a second upper surface positioned above the semiconductor substrate, wherein the first upper surface of the first gate structure is positioned at a first height level above a reference surface of the semiconductor substrate and the second upper surface of the second gate structure is positioned at a second height level above the reference surface of the semiconductor substrate, the first height level being greater than the second height level.

Abstract translation: 本文公开的新颖的集成电路产品的一个示例尤其包括横向FinFET器件，其包括具有位于半导体衬底上方的第一上表面的第一栅极结构和包括具有第二上表面的第二栅极结构的垂直FinFET器件 位于所述半导体衬底上方，其中所述第一栅极结构的所述第一上表面位于所述半导体衬底的参考表面上方的第一高度水平处，并且所述第二栅极结构的所述第二上表面位于所述第二栅极结构的第二高度水平 半导体衬底的参考表面，第一高度水平大于第二高度水平。