公开(公告)号：US09269621B2

公开(公告)日：2016-02-23

申请号：US14449314

申请日：2014-08-01

Applicant: GLOBALFOUNDRIES INC.

Inventor： Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III ,  Shom Ponoth ,  Chih-Chao Yang

IPC: H01L21/311 ,  H01L21/44 ,  H01L21/768 ,  H01L23/522

CPC classification number: H01L21/76897 ,  H01L21/76807 ,  H01L21/76808 ,  H01L21/76811 ,  H01L21/76819 ,  H01L21/76831 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76883 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A stack of a first metal line and a first dielectric cap material portion is formed within a line trench of first dielectric material layer. A second dielectric material layer is formed thereafter. A line trench extending between the top surface and the bottom surface of the second dielectric material layer is patterned. A photoresist layer is applied over the second dielectric material layer and patterned with a via pattern. An underlying portion of the first dielectric cap material is removed by an etch selective to the dielectric materials of the first and second dielectric material layer to form a via cavity that is laterally confined along the widthwise direction of the line trench and along the widthwise direction of the first metal line. A dual damascene line and via structure is formed, which includes a via structure that is laterally confined along two independent horizontal directions.

Abstract translation: 在第一介电材料层的线沟槽内形成第一金属线和第一介电帽材料部分的堆叠。 之后形成第二电介质材料层。 在第二介电材料层的顶表面和底表面之间延伸的线沟槽被图案化。 将光致抗蚀剂层施加在第二介电材料层上并用通孔图案构图。 通过对第一和第二介电材料层的介电材料的选择性蚀刻来去除第一电介质盖材料的下部，以形成沿着线沟槽的宽度方向横向限制并沿着宽度方向的 第一条金属线。 形成双镶嵌线和通孔结构，其包括沿着两个独立的水平方向横向限制的通孔结构。

公开(公告)号：US20150380262A1

公开(公告)日：2015-12-31

申请号：US14843085

申请日：2015-09-02

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Marc A. Bergendahl ,  David V. Horak ,  Charles W. Koburger, III ,  Shom Ponoth ,  Chih-Chao Yang

IPC: H01L21/308 ,  H01L21/3065

CPC classification number: H01L21/3088 ,  H01L21/2815 ,  H01L21/3065 ,  H01L21/3085 ,  H01L21/3086

Abstract: Fin structures and methods of manufacturing fin structures using a dual-material sidewall image transfer mask to enable patterning of sub-lithographic features is disclosed. The method of forming a plurality of fins includes forming a first set of fins having a first pitch. The method further includes forming an adjacent fin to the first set of fins. The adjacent fin and a nearest fin of the first set of fins have a second pitch larger than the first pitch. The first set of fins and the adjacent fin are sub-lithographic features formed using a sidewall image transfer process.

Abstract translation: 公开了使用双材料侧壁图像转印掩模制造翅片结构以实现亚光刻特征图案化的翅片结构和方法。 形成多个翅片的方法包括形成具有第一间距的第一组翅片。 该方法还包括形成与第一组翅片相邻的翅片。 相邻翅片和第一组翅片的最近的翅片具有比第一节距大的第二节距。 第一组翅片和相邻翅片是使用侧壁图像转移过程形成的亚光刻特征。

公开(公告)号：US20150061040A1

公开(公告)日：2015-03-05

申请号：US14538401

申请日：2014-11-11

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES, INC.

Inventor： Marc Adam Bergendahl ,  Kangguo Cheng ,  David Vaclav Horak ,  Ali Khakifirooz ,  Shom Ponoth ,  Theodorus Eduardus Standaert ,  Chih-Chao Yang ,  Charles William Koburger, III ,  Xiuyu Cai ,  Ruilong Xie

IPC: H01L27/088 ,  H01L29/06

CPC classification number: H01L27/0886 ,  H01L29/0649 ,  H01L29/6681 ,  H01L29/7855

Abstract: Embodiments of the present invention provide a method of forming semiconductor structure. The method includes forming a set of device features on top of a substrate; forming a first dielectric layer directly on top of the set of device features and on top of the substrate, thereby creating a height profile of the first dielectric layer measured from a top surface of the substrate, the height profile being associated with a pattern of an insulating structure that fully surrounds the set of device features; and forming a second dielectric layer in areas that are defined by the pattern to create the insulating structure. A structure formed by the method is also disclosed.

Abstract translation: 本发明的实施例提供一种形成半导体结构的方法。 该方法包括在衬底的顶部上形成一组器件特征; 在所述组装置特征的顶部直接形成第一介电层，并在所述基板的顶部上形成第一电介质层，从而产生从所述基板的顶表面测量的所述第一电介质层的高度分布，所述高度分布与所述基板的图案相关联 完全围绕设备特征的绝缘结构; 以及在由所述图案限定的区域中形成第二电介质层以形成所述绝缘结构。 还公开了通过该方法形成的结构。

公开(公告)号：US10090240B2

公开(公告)日：2018-10-02

申请号：US15172551

申请日：2016-06-03

Applicant: GLOBALFOUNDRIES INC.

Inventor： Baozhen Li ,  Chih-Chao Yang ,  Keith Kwong Hon Wong

IPC: H01L23/522 ,  H01L21/768 ,  H01L49/02 ,  H01L23/532

Abstract: Various embodiments include methods and integrated circuit structures. In some cases, a method of forming an integrated circuit structure can include: forming an opening in a low-k dielectric layer; filling the opening with a high-k dielectric material; patterning the low-k dielectric layer outside of the opening and the high-k dielectric layer to form an interconnect opening within the low-k dielectric layer and a capacitor opening within the high-k dielectric layer; and filling the interconnect opening and the capacitor opening with a metal to form an interconnect in the low-k dielectric layer and a capacitor in the high-k dielectric layer.

公开(公告)号：US09379198B2

公开(公告)日：2016-06-28

申请号：US14494699

申请日：2014-09-24

Applicant: GLOBALFOUNDRIES INC.

Inventor： Chih-Chao Yang ,  David V. Horak ,  Charles W. Koburger ,  Shom Ponoth

IPC: H01L29/423 ,  H01L29/49 ,  H01L29/51 ,  H01L21/28 ,  H01L21/768 ,  H01L29/78

CPC classification number: H01L29/42372 ,  H01L21/28247 ,  H01L21/76834 ,  H01L21/7685 ,  H01L21/76856 ,  H01L21/76888 ,  H01L21/76897 ,  H01L29/495 ,  H01L29/517 ,  H01L29/78

Abstract: An integrated circuit structure with a selectively formed and at least partially oxidized metal cap over a gate. In one embodiment, an integrated circuit structure has: a substrate; a metal gate located over the substrate; at least one liner layer over the substrate and substantially surrounding the metal gate; and an at least partially oxidized etch stop layer located directly over the metal gate, the etch stop layer including at least one of cobalt (Co), manganese (Mn), tungsten (W), iridium (Ir), rhodium (Rh) or ruthenium (Ru).

Abstract translation: 一种在栅极上具有选择性地形成和至少部分氧化的金属盖的集成电路结构。 在一个实施例中，集成电路结构具有：基板; 位于衬底上方的金属栅极; 至少一个衬底层，并且基本上围绕着金属栅极; 以及位于金属栅极正上方的至少部分氧化的蚀刻停止层，所述蚀刻停止层包括钴（Co），锰（Mn），钨（W），铱（Ir），铑（Rh）或 钌（Ru）。

公开(公告)号：US20140191296A1

公开(公告)日：2014-07-10

申请号：US13735315

申请日：2013-01-07

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES, INC.

Inventor： Marc Adam Bergendahl ,  Kangguo Cheng ,  David Vaclav Horak ,  Ali Khakifirooz ,  Shom Ponoth ,  Theodorus Eduardus Standaert ,  Chih-Chao Yang ,  Charles William Koburger, III ,  Xiuyu Cai ,  Ruilong Xie

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L27/0886 ,  H01L29/0649 ,  H01L29/6681 ,  H01L29/7855

Abstract: Embodiments of the present invention provide a method of forming semiconductor structure. The method includes forming a set of device features on top of a substrate; forming a first dielectric layer directly on top of the set of device features and on top of the substrate, thereby creating a height profile of the first dielectric layer measured from a top surface of the substrate, the height profile being associated with a pattern of an insulating structure that fully surrounds the set of device features; and forming a second dielectric layer in areas that are defined by the pattern to create the insulating structure. A structure formed by the method is also disclosed.

Abstract translation: 本发明的实施例提供一种形成半导体结构的方法。 该方法包括在衬底的顶部上形成一组器件特征; 在所述一组装置特征的顶部直接形成第一介电层，并且在所述基板的顶部上形成第一电介质层，从而产生从所述基板的顶表面测量的所述第一介电层的高度分布，所述高度分布与所述基板的图案相关联 完全围绕设备特征的绝缘结构; 以及在由所述图案限定的区域中形成第二电介质层以形成所述绝缘结构。 还公开了通过该方法形成的结构。

公开(公告)号：US09660030B2

公开(公告)日：2017-05-23

申请号：US14473033

申请日：2014-08-29

Applicant: GLOBALFOUNDRIES INC.

Inventor： Shom Ponoth ,  Marc A. Bergendahl ,  Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III ,  Chih-Chao Yang

IPC: H01L29/165 ,  H01L21/338 ,  H01L29/08 ,  H01L29/66 ,  H01L21/28 ,  H01L21/02 ,  H01L29/78

CPC classification number: H01L29/0847 ,  H01L21/0257 ,  H01L21/02636 ,  H01L21/28008 ,  H01L21/28114 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66795 ,  H01L29/785

Abstract: A dielectric disposable gate structure can be formed across a semiconductor material portion, and active semiconductor regions are formed within the semiconductor material portion. Raised active semiconductor regions are grown over the active semiconductor regions while the dielectric disposable gate structure limits the extent of the raised active semiconductor regions. A planarization dielectric layer is formed over the raised active semiconductor regions. In one embodiment, the dielectric disposable gate structure is removed, and a dielectric gate spacer can be formed by conversion of surface portions of the raised active semiconductor regions around a gate cavity. Alternately, an etch mask layer overlying peripheral portions of the disposable gate structure can be formed, and a gate cavity and a dielectric spacer can be formed by anisotropically etching an unmasked portion of the dielectric disposable gate structure. A replacement gate structure can be formed in the gate cavity.

公开(公告)号：US09392690B2

公开(公告)日：2016-07-12

申请号：US14177530

申请日：2014-02-11

Applicant: GLOBALFOUNDRIES INC.

Inventor： Fenton R. McFeely ,  Chih-Chao Yang

IPC: H05K1/09 ,  H01L21/768 ,  H01L23/532

CPC classification number: H05K1/09 ,  H01L21/76846 ,  H01L21/76864 ,  H01L21/76873 ,  H01L21/76883 ,  H01L23/53238 ,  H01L2221/1089 ,  H01L2924/0002 ,  Y10T29/49126 ,  Y10T29/49165 ,  H01L2924/00

Abstract: Techniques for improving the conductivity of copper (Cu)-filled vias are provided. In one aspect, a method of fabricating a Cu-filled via is provided. The method includes the following steps. A via is etched in a dielectric. The via is lined with a diffusion barrier. A thin ruthenium (Ru) layer is conformally deposited onto the diffusion barrier. A thin seed Cu layer is deposited on the Ru layer. A first anneal is performed to increase a grain size of the seed Cu layer. The via is filled with additional Cu. A second anneal is performed to increase the grain size of the additional Cu.

Abstract translation: 提供了提高铜（Cu）填充通孔电导率的技术。 一方面，提供了制造填充铜的通孔的方法。 该方法包括以下步骤。 在电介质中蚀刻通孔。 通孔内有一个扩散屏障。 薄的钌（Ru）层共形沉积到扩散阻挡层上。 在Ru层上沉积薄的种子Cu层。 进行第一退火以增加种子Cu层的晶粒尺寸。 通孔填充有额外的铜。 进行第二次退火以增加附加Cu的晶粒尺寸。

公开(公告)号：US09263290B2

公开(公告)日：2016-02-16

申请号：US14843085

申请日：2015-09-02

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Marc A. Bergendahl ,  David V. Horak ,  Charles W. Koburger, III ,  Shom Ponoth ,  Chih-Chao Yang

IPC: H01L21/311 ,  H01L21/308 ,  H01L21/3065

CPC classification number: H01L21/3088 ,  H01L21/2815 ,  H01L21/3065 ,  H01L21/3085 ,  H01L21/3086

Abstract: Fin structures and methods of manufacturing fin structures using a dual-material sidewall image transfer mask to enable patterning of sub-lithographic features is disclosed. The method of forming a plurality of fins includes forming a first set of fins having a first pitch. The method further includes forming an adjacent fin to the first set of fins. The adjacent fin and a nearest fin of the first set of fins have a second pitch larger than the first pitch. The first set of fins and the adjacent fin are sub-lithographic features formed using a sidewall image transfer process.

公开(公告)号：US08941156B2

公开(公告)日：2015-01-27

申请号：US13735315

申请日：2013-01-07

Applicant: International Business Machines Corporation ,  GlobalFoundries, Inc.

Inventor： Marc Adam Bergendahl ,  Kangguo Cheng ,  David Vaclav Horak ,  Ali Khakifirooz ,  Shom Ponoth ,  Theodorus Eduardus Standaert ,  Chih-Chao Yang ,  Charles William Koburger, III ,  Xiuyu Cai ,  Ruilong Xie

IPC: H01L29/78

CPC classification number: H01L27/0886 ,  H01L29/0649 ,  H01L29/6681 ,  H01L29/7855

Abstract: Embodiments of the present invention provide a method of forming semiconductor structure. The method includes forming a set of device features on top of a substrate; forming a first dielectric layer directly on top of the set of device features and on top of the substrate, thereby creating a height profile of the first dielectric layer measured from a top surface of the substrate, the height profile being associated with a pattern of an insulating structure that fully surrounds the set of device features; and forming a second dielectric layer in areas that are defined by the pattern to create the insulating structure. A structure formed by the method is also disclosed.

Abstract translation: 本发明的实施例提供一种形成半导体结构的方法。 该方法包括在衬底的顶部上形成一组器件特征; 在所述组装置特征的顶部直接形成第一介电层，并在所述基板的顶部上形成第一电介质层，从而产生从所述基板的顶表面测量的所述第一电介质层的高度分布，所述高度分布与所述基板的图案相关联 完全围绕设备特征的绝缘结构; 以及在由所述图案限定的区域中形成第二电介质层以形成所述绝缘结构。 还公开了通过该方法形成的结构。