公开(公告)号：US10418364B2

公开(公告)日：2019-09-17

申请号：US15252995

申请日：2016-08-31

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Peter Baars ,  Hans-Jürgen Thees

IPC: H01L27/108 ,  H01L21/285 ,  H01L21/762 ,  H01L21/84 ,  H01L27/12 ,  H01L29/06 ,  H01L29/08 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/45 ,  H01L29/66 ,  H01L29/78 ,  H01L49/02 ,  H01L21/768 ,  H01L23/485 ,  H01L27/06

Abstract: A semiconductor device structure is disclosed including a semiconductor-on-insulator (SOI) substrate, the SOI substrate comprising a semiconductor layer, a substrate material and a buried insulating material layer positioned between the semiconductor layer and the substrate material, a trench isolation structure positioned in at least a portion of the SOI substrate, the trench isolation structure defining a first region in the SOI substrate, and a capacitor device formed in the first region, the capacitor device comprising a first electrode formed by a conductive layer portion formed in the first region on the buried insulating material layer, the conductive layer portion at least partially replacing the semiconductor layer in the first region, a second electrode formed over the first electrode, and an insulating material formed between the first electrode and the second electrode.

公开(公告)号：US20190148245A1

公开(公告)日：2019-05-16

申请号：US15810557

申请日：2017-11-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Peter Baars ,  Rick Carter ,  Vikrant Chauhan ,  George Jonathan Kluth ,  Anurag Mittal ,  David Pritchard ,  Mahbub Rashed

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/417 ,  H01L27/12 ,  H01L29/49

CPC classification number: H01L21/823871 ,  H01L21/823814 ,  H01L21/823878 ,  H01L27/0922 ,  H01L27/1203 ,  H01L27/1207 ,  H01L29/41783 ,  H01L29/4941 ,  H01L2924/0002

Abstract: A method of forming contacts includes forming a plurality of transistor devices separated by shallow trench insulator regions, the transistor devices each comprising a semiconductor substrate, a buried insulator layer on the semiconductor bulk substrate, a semiconductor layer on the buried insulator layer, a high-k metal gate stack on the semiconductor layer and a gate electrode above the high-k metal gate stack, raised source/drain regions on the semiconductor layer, and a silicide contact layer above the raised source/drain regions and the gate electrode, providing an interlayer dielectric stack on the silicide contact layer and planarizing the interlayer dielectric stack, patterning a plurality of contacts through the interlayer dielectric stack onto the raised source/drain regions, and, for at least some of the contacts, patterning laterally extended contact regions above the contacts, the laterally extended contact regions extending over shallow trench insulator regions neighboring the corresponding raised source/drain regions.

公开(公告)号：US10062619B2

公开(公告)日：2018-08-28

申请号：US15232090

申请日：2016-08-09

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hans-Juergen Thees ,  Peter Baars

IPC: H01L21/00 ,  H01L21/84 ,  H01L21/311 ,  H01L21/265 ,  H01L27/12 ,  H01L21/8238 ,  H01L29/78

CPC classification number: H01L21/84 ,  H01L21/26513 ,  H01L21/2652 ,  H01L21/31111 ,  H01L21/823814 ,  H01L21/823842 ,  H01L21/823864 ,  H01L27/1203 ,  H01L29/6656 ,  H01L29/7834

Abstract: A method of forming a semiconductor device includes providing a silicon-on-insulator substrate comprising a semiconductor bulk substrate, a buried insulation layer formed on the semiconductor bulk substrate and a semiconductor layer formed on the buried insulation layer, providing at least one N-type metal-oxide semiconductor gate structure being an NZG gate structure having a gate insulation layer over the semiconductor layer and at least one P-type metal-oxide semiconductor gate structure being a PZG gate structure having a gate insulation layer over the semiconductor layer, the NZG and PZG gate structures being electrically separated from each other.

公开(公告)号：US09960184B2

公开(公告)日：2018-05-01

申请号：US15645686

申请日：2017-07-10

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jan Hoentschel ,  Peter Baars ,  Hans-Peter Moll

IPC: H01L27/12 ,  H01L29/94 ,  H01L27/06 ,  H01L21/762 ,  H01L21/84 ,  H01L29/786 ,  H01L49/02 ,  H01L29/06 ,  H01L21/265 ,  H01L21/285 ,  H01L27/108

CPC classification number: H01L27/1207 ,  H01L21/26513 ,  H01L21/28518 ,  H01L21/76264 ,  H01L21/84 ,  H01L27/0629 ,  H01L27/10829 ,  H01L27/1085 ,  H01L27/1087 ,  H01L28/60 ,  H01L29/0649 ,  H01L29/786 ,  H01L29/94

Abstract: A semiconductor device includes a semiconductor-on-insulator (SOI) wafer having a semiconductor substrate, a buried insulating layer positioned above the semiconductor substrate, and a semiconductor layer positioned above the buried insulating layer. A shallow trench isolation (STI) structure is positioned in the SOI wafer and separates a first region of the SOI wafer from a second region of the SOI wafer, wherein the semiconductor layer is not present above the buried insulating layer in the first region, and wherein the buried insulating layer and the semiconductor layer are not present in at least a first portion of the second region adjacent to the STI structure. A dielectric layer is positioned above the buried insulating layer in the first region, and a conductive layer is positioned above the dielectric layer in the first region.

公开(公告)号：US09929148B1

公开(公告)日：2018-03-27

申请号：US15439444

申请日：2017-02-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Peter Baars ,  Frank Jakubowski

IPC: H01L23/52 ,  H01L27/06 ,  H01L29/06 ,  H01L23/535 ,  H01L29/417 ,  H01L23/31 ,  H01L29/49 ,  H01L49/02 ,  H01L21/762 ,  H01L21/84 ,  H01L21/3213 ,  H01L21/321

CPC classification number: H01L27/0629 ,  H01L21/76283 ,  H01L21/84 ,  H01L23/3178 ,  H01L23/535 ,  H01L27/108 ,  H01L27/1203 ,  H01L28/60 ,  H01L29/0649 ,  H01L29/41783 ,  H01L29/4916 ,  H01L29/495

Abstract: The present disclosure provides semiconductor devices and manufacturing techniques in which a buried capacitive structure may be provided at the level of the buried insulating layer of an SOI device, thereby providing reduced process complexity compared to conventional strategies, while still preserving superior routing capabilities above the buried capacitive structures.

公开(公告)号：US20170271484A1

公开(公告)日：2017-09-21

申请号：US15498652

申请日：2017-04-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Peter Baars ,  Juergen Faul

IPC: H01L29/66 ,  H01L21/8234 ,  H01L21/266 ,  H01L27/11521 ,  H01L21/768

CPC classification number: H01L29/66825 ,  H01L21/266 ,  H01L21/7684 ,  H01L21/76883 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823821 ,  H01L21/823828 ,  H01L27/0886 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11536 ,  H01L27/11543 ,  H01L29/42324 ,  H01L29/42328 ,  H01L29/66545 ,  H01L29/6681 ,  H01L29/785 ,  H01L29/788 ,  H01L29/7881

Abstract: A method of manufacturing a flash memory cell is provided including forming a plurality of semiconductor fins on a semiconductor substrate, forming floating gates for a sub-set of the plurality of semiconductor fins and forming a first insulating layer between the plurality of semiconductor fins. The first insulating layer is recessed to a height less than the height of the plurality of semiconductor fins and sacrificial gates are formed over the sub-set of the plurality of semiconductor fins. A second insulating layer is formed between the sacrificial gates and, after that, the sacrificial gates are removed. Recesses are formed in the first insulating layer and sense gates and control gates are formed in the recesses for the sub-set of the plurality of semiconductor fins. The first and second insulating layers may be oxide layers.

公开(公告)号：US20170148919A1

公开(公告)日：2017-05-25

申请号：US15426728

申请日：2017-02-07

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Peter Baars ,  Carsten Grass

IPC: H01L29/78 ,  H01L29/51 ,  H01L21/28 ,  H01L29/66 ,  H01L27/1159 ,  H01L27/092 ,  H01L21/8238

CPC classification number: H01L29/78391 ,  H01L21/28185 ,  H01L21/28291 ,  H01L21/823462 ,  H01L21/823857 ,  H01L27/088 ,  H01L27/092 ,  H01L27/0922 ,  H01L27/1159 ,  H01L27/11592 ,  H01L29/513 ,  H01L29/516 ,  H01L29/517 ,  H01L29/66545

Abstract: A semiconductor circuit element includes a first semiconductor device positioned in and above a first active region of a semiconductor substrate and a second semiconductor device positioned in and above a second active region of the semiconductor substrate. The first semiconductor device includes a first gate structure having a first gate dielectric layer that includes a first high-k material, and the second semiconductor device includes a second gate structure having a second gate dielectric layer that includes a ferroelectric material that is different from the first high-k material.

公开(公告)号：US20170062438A1

公开(公告)日：2017-03-02

申请号：US15146979

申请日：2016-05-05

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hans-Peter Moll ,  Peter Baars

IPC: H01L27/11 ,  H01L29/417 ,  H01L29/49 ,  H01L29/45 ,  H01L29/06 ,  H01L27/12 ,  H01L29/08 ,  H01L29/66

CPC classification number: H01L29/4958 ,  H01L29/41783 ,  H01L29/66515 ,  H01L29/6656

Abstract: A method of manufacturing a semiconductor device is provided including forming a gate electrode layer over a semiconductor substrate, forming a sidewall spacer at a sidewall of the gate electrode layer, forming a raised source/drain region over the semiconductor substrate and adjacent to the sidewall spacer, removing a portion of the sidewall spacer, thereby exposing a portion of the sidewall of the gate electrode layer, and forming an electrically conductive layer electrically connecting the exposed portion of the sidewall of the gate electrode layer and the source/drain region.

Abstract translation: 提供了一种制造半导体器件的方法，包括在半导体衬底上形成栅电极层，在栅极电极层的侧壁处形成侧壁间隔物，在半导体衬底上形成凸起的源极/漏极区域，并且邻近于侧壁间隔物 去除所述侧壁间隔物的一部分，从而暴露所述栅电极层的侧壁的一部分，以及形成电连接所述栅极电极层的侧壁的暴露部分和所述源极/漏极区域的导电层。

公开(公告)号：US09425189B1

公开(公告)日：2016-08-23

申请号：US14813292

申请日：2015-07-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hans-Peter Moll ,  Peter Baars

IPC: H01L27/01 ,  H01L31/0392 ,  H01L27/02 ,  H01L29/786 ,  H01L29/06 ,  H01L29/45 ,  H01L29/423 ,  H01L21/02 ,  H01L29/417 ,  H01L21/285 ,  H01L21/308 ,  H01L29/66 ,  H01L27/12 ,  H01L21/8234

CPC classification number: H01L21/823481 ,  H01L21/743 ,  H01L21/823418 ,  H01L21/823475 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/41783 ,  H01L29/42356 ,  H01L29/45 ,  H01L29/66742 ,  H01L29/78603

Abstract: The present disclosure provides a semiconductor device including an SOI substrate comprising an active semiconductor layer disposed on a buried insulating material layer, which is in turn formed on a base semiconductor material. The semiconductor device further includes a gate structure formed on the active semiconductor layer, source/drain regions provided at opposing sides of the gate structure, and a contact structure having contact elements for contacting the source/drain regions. Herein, the contact elements are disposed at opposing sides of the gate structure and are in alignment therewith. Furthermore, one of the contact elements extends through the buried insulating material layer and is in electrical contact with the base semiconductor material.

Abstract translation: 本公开提供了一种包括SOI衬底的半导体器件，SOI衬底包括设置在掩埋绝缘材料层上的有源半导体层，所述有源半导体层又形成在基极半导体材料上。 半导体器件还包括形成在有源半导体层上的栅极结构，设置在栅极结构的相对侧处的源极/漏极区域和具有用于接触源极/漏极区域的接触元件的接触结构。 这里，接触元件设置在栅极结构的相对侧并且与其对准。 此外，一个接触元件延伸穿过掩埋绝缘材料层并与基底半导体材料电接触。

公开(公告)号：US09385232B2

公开(公告)日：2016-07-05

申请号：US14521939

申请日：2014-10-23

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hans-Peter Moll ,  Peter Baars ,  Jan Hoentschel

IPC: H01L21/00 ,  H01L29/78 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L29/7848 ,  H01L21/76224 ,  H01L21/823878 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66568 ,  H01L29/66628 ,  H01L29/66772 ,  H01L29/7838 ,  H01L29/7849 ,  H01L29/78603 ,  H01L29/78639 ,  H01L29/78654

Abstract: The present disclosure provides in some aspects a semiconductor device and a method of forming a semiconductor device. According to some illustrative embodiments herein, the semiconductor device includes an active region formed in a semiconductor substrate, a gate structure disposed over the active region, source/drain regions formed in the active region in alignment with the gate structure, and an insulating material region buried into the active region under the gate structure, wherein the insulating material region is surrounded by the active region and borders a channel region in the active region below the gate structure along a depth direction of the active region.

Abstract translation: 本公开在一些方面提供半导体器件和形成半导体器件的方法。 根据这里的一些说明性实施例，半导体器件包括形成在半导体衬底中的有源区，设置在有源区上的栅极结构，形成在与栅极结构对准的有源区中的源/漏区，以及绝缘材料区 埋入栅极结构下的有源区，其中绝缘材料区域被有源区域包围，并且沿着有源区域的深度方向与栅极结构下方的有源区域中的沟道区域相邻。