公开(公告)号：US10790198B2

公开(公告)日：2020-09-29

申请号：US16058494

申请日：2018-08-08

Applicant: GLOBALFOUNDRIES INC.

Inventor： Fuad H. Al-Amoody ,  Yiheng Xu ,  Rishikesh Krishnan

IPC: H01L29/06 ,  H01L21/8234 ,  H01L21/762 ,  H01L21/02

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to fin structures and methods of manufacture. The structure includes: a plurality of fin structures formed of substrate material; a semiconductor material located between selected fin structures of the plurality of fin structures; and isolation regions within spaces between the plurality of fin structures.

公开(公告)号：US20190027556A1

公开(公告)日：2019-01-24

申请号：US15656574

申请日：2017-07-21

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jiehui Shu ,  Rishikesh Krishnan ,  Jinping Liu ,  Yiheng Xu ,  Joseph F. Shepard, JR.

IPC: H01L29/06 ,  H01L21/762 ,  H01L21/02 ,  H01L21/3105

Abstract: A method of forming a shallow trench isolation (STI) for an integrated circuit (IC) structure to mitigate fin bending disclosed. The method may include forming a first insulator layer in a first portion of an opening in a substrate by a bottom-up atomic layer deposition (ALD) process; and forming a second insulator layer on the first insulator layer in a second portion of the opening. The opening may be position between a set of fins in the substrate. The method may further include forming an oxide liner in the opening before the forming the first insulator layer. The second insulator layer may be formed by deposition using a flowable chemical vapor deposition (FCVD) process, high aspect ratio process (HARP), high-density plasma chemical vapor deposition (HDP CVD) process, or any other conventional insulator material deposition process.

公开(公告)号：US09536985B2

公开(公告)日：2017-01-03

申请号：US14499356

申请日：2014-09-29

Applicant: GLOBALFOUNDRIES INC.

Inventor： Michael P. Chudzik ,  Brian J. Greene ,  Eric C. T. Harley ,  Judson R. Holt ,  Yue Ke ,  Rishikesh Krishnan ,  Renee T. Mo ,  Yinxiao Yang

IPC: H01L29/66

CPC classification number: H01L29/66795 ,  H01L29/7848

Abstract: A method for producing a semiconductor structure, as well as a semiconductor structure, that uses a partial removal of an insulating layer around a semiconductor fin, and subsequently epitaxially growing an additional semiconductor material in the exposed regions, while maintaining the shape of the fin with the insulating layer.

Abstract translation: 一种用于制造半导体结构的方法以及半导体结构，其使用半导体鳍周围的绝缘层的部分去除，并且随后在暴露区域中外延生长另外的半导体材料，同时保持鳍的形状，同时保持鳍的形状 绝缘层。

公开(公告)号：US09577100B2

公开(公告)日：2017-02-21

申请号：US14305543

申请日：2014-06-16

Applicant: GLOBALFOUNDRIES INC.

Inventor： Kangguo Cheng ,  Michael P. Chudzik ,  Eric C. Harley ,  Judson R. Holt ,  Yue Ke ,  Rishikesh Krishnan ,  Kern Rim ,  Henry K. Utomo

IPC: H01L27/12 ,  H01L29/78 ,  H01L29/66 ,  H01L29/161 ,  H01L29/10 ,  B82Y10/00 ,  H01L29/423 ,  H01L29/775 ,  H01L29/06 ,  H01L21/306 ,  H01L29/165

CPC classification number: H01L29/7851 ,  B82Y10/00 ,  H01L21/30604 ,  H01L29/0673 ,  H01L29/1037 ,  H01L29/161 ,  H01L29/165 ,  H01L29/42376 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/6681 ,  H01L29/775 ,  H01L29/7848 ,  H01L29/78696

Abstract: A semiconductor device including at least one suspended channel structure of a silicon including material, and a gate structure present on the suspended channel structure. At least one gate dielectric layer is present surrounding the suspended channel structure, and at least one gate conductor is present on the at least one gate dielectric layer. Source and drain structures may be composed of a silicon and germanium including material. The source and drain structures are in contact with the source and drain region ends of the suspended channel structure through a silicon cladding layer.

Abstract translation: 一种半导体器件，包括至少一个包含硅的悬浮沟道结构，以及存在于悬挂沟道结构上的栅极结构。 至少一个栅极电介质层存在于悬置沟道结构周围，并且至少一个栅极导体存在于至少一个栅极电介质层上。 源极和漏极结构可以由包括硅和锗的材料组成。 源极和漏极结构通过硅包覆层与悬浮沟道结构的源极和漏极端部接触。

公开(公告)号：US09269607B2

公开(公告)日：2016-02-23

申请号：US14306598

申请日：2014-06-17

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Edward Engbrecht ,  Donghun Kang ,  Rishikesh Krishnan ,  Oh-jung Kwon ,  Karen A. Nummy

IPC: H01L21/30 ,  H01L21/762 ,  H01L21/308 ,  H01L21/321 ,  H01L29/06 ,  H01L21/66

CPC classification number: H01L21/76227 ,  H01L21/302 ,  H01L21/308 ,  H01L21/3081 ,  H01L21/3212 ,  H01L22/12 ,  H01L29/0603 ,  H01L29/945

Abstract: Embodiments of the present invention provide structures and methods for controlling stress in semiconductor wafers during fabrication. Features such as deep trenches (DTs) used in circuit elements such as trench capacitors impart stress on a wafer that is proportional to the surface area of the DTs. In embodiments, a corresponding pattern of dummy (non-functional) DTs is formed on the back side of the wafer to counteract the electrically functional DTs formed on the front side of a wafer. In some embodiments, the corresponding pattern on the back side is a mirror pattern that matches the functional (front side) pattern in size, placement, and number. By creating the minor pattern on both sides of the wafer, the stresses on the front and back of the wafer are in balance. This helps reduce topography issues such as warping that can cause problems during wafer fabrication.

Abstract translation: 本发明的实施例提供了在制造期间控制半导体晶片中的应力的结构和方法。 诸如沟槽电容器的电路元件中使用的诸如深沟槽（DT）的特征赋予与DT的表面积成比例的晶片上的应力。 在实施例中，虚拟（非功能）DT的相应图案形成在晶片的背面，以抵消形成在晶片前侧上的电功能DT。 在一些实施例中，背面上的对应图案是与尺寸，布局和数量上的功能（前侧）图案相匹配的镜面图案。 通过在晶片的两侧形成次要图案，晶片正面和背面的应力平衡。 这有助于减少在晶圆制造过程中可能导致问题的翘曲等形貌问题。

公开(公告)号：US10886178B2

公开(公告)日：2021-01-05

申请号：US16109258

申请日：2018-08-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Tek Po Rinus Lee ,  Annie Levesque ,  Qun Gao ,  Hui Zang ,  Rishikesh Krishnan ,  Bharat Krishnan ,  Curtis Durfee

IPC: H01L29/167 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/78 ,  H01L23/532 ,  H01L21/02 ,  H01L29/40 ,  H01L23/535

Abstract: A device including a triple-layer EPI stack including SiGe, Ge, and Si, respectively, with Ga confined therein, and method of production thereof. Embodiments include an EPI stack including a SiGe layer, a Ge layer, and a Si layer over a plurality of fins, the EPI stack positioned between and over a portion of sidewall spacers, wherein the Si layer is a top layer capping the Ge layer, and wherein the Ge layer is a middle layer capping the SiGe layer underneath; and a Ga layer in a portion of the Ge layer between the SiGe layer and the Si layer.

公开(公告)号：US10211045B1

公开(公告)日：2019-02-19

申请号：US15878502

申请日：2018-01-24

Applicant: GLOBALFOUNDRIES INC.

Inventor： Rishikesh Krishnan ,  Joseph K. Kassim ,  Bharat V. Krishnan ,  Joseph F. Shepard, Jr. ,  Rinus Tek Po Lee ,  Yiheng Xu

IPC: H01L21/02 ,  H01L21/3105 ,  H01L29/06 ,  H01L21/762 ,  H01L27/088

Abstract: An insulator is formed by flowable chemical vapor deposition (FCVD) process. The insulator is cured by exposing the insulator to ultraviolet light while flowing ozone over the insulator to produce a cured insulator. The curing process forms nitrogen, hydrogen, nitrogen monohydride, or hydroxyl-rich atomic clusters in the insulator. Following the curing process, these methods select wavelengths of microwave radiation (that will be subsequently used during annealing) so that such wavelengths excite the nitrogen, hydrogen, nitrogen monohydride, or hydroxyl-rich atomic clusters. Then, these methods anneal the cured insulator by exposing the cured insulator to microwave radiation in an inert (e.g., non-oxidizing) ambient atmosphere, at a temperature below 500° C., so as to increase the density of the cured insulator.