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    Creating An Embedded ReRam Memory From A High-K Metal Gate Transistor Structure
    3.
    发明申请
    Creating An Embedded ReRam Memory From A High-K Metal Gate Transistor Structure 审中-公开
    从高K金属栅晶体管结构创建嵌入式ReRam存储器

    公开(公告)号：US20150236260A1

    公开(公告)日：2015-08-20

    申请号：US14702374

    申请日：2015-05-01

    Applicant: Intermolecular Inc.

    Inventor： Dipankar Pramanik ,  Tony P. Chiang ,  David E. Lazovsky

    IPC: H01L45/00 ,  H01L27/24

    CPC classification number: H01L45/1658 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/16 ,  H01L45/1683

    Abstract: An embodiment of the present invention sets forth an embedded resistive memory cell that includes a first stack of deposited layers, a second stack of deposited layers, a first electrode disposed under a first portion of the first stack, and a second electrode disposed under a second portion of the first stack and extending from under the second portion of the first stack to under the second stack. The second electrode is disposed proximate to the first electrode within the embedded resistive memory cell. The first stack of deposited layers includes a dielectric layer, a high-k dielectric layer disposed above the dielectric layer, and a metal layer disposed above the high-k dielectric layer. The second stack of deposited layers includes a high-k dielectric layer formed simultaneously with the high-k dielectric layer included in the first stack, and a metal layer disposed above the high-k dielectric layer.

    Abstract translation: 本发明的实施例提出了一种嵌入式电阻式存储单元，其包括沉积层的第一堆叠，沉积层的第二堆叠，设置在第一堆叠的第一部分下方的第一电极和设置在第二堆叠下的第二电极的第二电极 第一堆叠的部分并且从第一堆叠的第二部分下方延伸到第二堆叠下方。 第二电极设置在嵌入式电阻式存储单元内靠近第一电极。 第一堆沉积层包括介电层，设置在电介质层上方的高k电介质层和设置在高k电介质层上方的金属层。 第二层沉积层包括与包含在第一堆叠中的高k电介质层同时形成的高k电介质层和设置在高k电介质层上方的金属层。

    High throughput quantum efficiency combinatorial characterization tool and method for combinatorial solar test substrates
    4.
    发明授权
    High throughput quantum efficiency combinatorial characterization tool and method for combinatorial solar test substrates 有权
    用于组合太阳能测试基板的高通量量子效率组合表征工具和方法

    公开(公告)号：US09103871B2

    公开(公告)日：2015-08-11

    申请号：US14077545

    申请日：2013-11-12

    Applicant: Intermolecular, Inc.

    Inventor： Yun Wang ,  Tony P. Chiang ,  Chi-I Lang

    IPC: G01R31/26 ,  G01N21/55 ,  H02S50/10

    CPC classification number: G01R31/26 ,  G01N21/55 ,  G01R31/2607 ,  H02S50/10

    Abstract: Simultaneous measurement of an internal quantum efficiency and an external quantum efficiency of a solar cell using an emitter that emits light; a three-way beam splitter that splits the light into solar cell light and reference light, wherein the solar cell light strikes the solar cell; a reference detector that detects the reference light; a reflectance detector that detects reflectance light, wherein the reflectance light comprises a portion of the solar cell light reflected off the solar cell; a source meter operatively coupled to the solar cell; a multiplexer operatively coupled to the solar cell, the reference detector, and the reflectance detector; and a computing device that simultaneously computes the internal quantum efficiency and the external quantum efficiency of the solar cell.

    Abstract translation: 使用发射光的同时测量太阳能电池的内部量子效率和外部量子效率; 三光束分离器，其将光分解成太阳能电池光和参考光，其中太阳能电池光照射到太阳能电池; 检测参考光的参考检测器; 反射光检测器，其检测反射光，其中所述反射光包括从太阳能电池反射的太阳能电池光的一部分; 可操作地耦合到太阳能电池的源计量器; 可操作地耦合到太阳能电池，参考检测器和反射检测器的多路复用器; 以及同时计算太阳能电池的内部量子效率和外部量子效率的计算装置。

    Sequential atomic layer deposition of electrodes and resistive switching components
    7.
    发明授权
    Sequential atomic layer deposition of electrodes and resistive switching components 有权
    电极和电阻式开关元件的顺序原子层沉积

    公开(公告)号：US08980766B2

    公开(公告)日：2015-03-17

    申请号：US14327774

    申请日：2014-07-10

    Applicant: Intermolecular Inc. ,  Kabushiki Kaisha Toshiba ,  SanDisk 3D LLC

    Inventor： Yun Wang ,  Tony P. Chiang ,  Tim Minvielle ,  Takeshi Yamaguchi

    IPC: H01L21/68 ,  H01L45/00 ,  H01L27/24

    CPC classification number: H01L45/145 ,  H01L27/2481 ,  H01L45/08 ,  H01L45/10 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/16 ,  H01L45/1616

    Abstract: Provided are methods of forming nonvolatile memory elements using atomic layer deposition techniques, in which at least two different layers of a memory element are deposited sequentially and without breaking vacuum in a deposition chamber. This approach may be used to prevent oxidation of various materials used for electrodes without a need for separate oxygen barrier layers. A combination of signal lines and resistive switching layers may be used to cap the electrodes and to minimize their oxidation. As such, fewer layers are needed in a memory element. Furthermore, atomic layer deposition allows more precise control of electrode thicknesses. In some embodiments, a thickness of an electrode may be less than 50 Angstroms. Overall, atomic layer deposition of electrodes and resistive switching layers lead to smaller thicknesses of entire memory elements making them more suitable for low aspect ratio features of advanced nodes.

    Abstract translation: 提供了使用原子层沉积技术形成非易失性存储元件的方法，其中存储元件的至少两个不同层顺次沉积并且在沉积室中不破坏真空。 该方法可以用于防止用于电极的各种材料的氧化，而不需要单独的氧阻隔层。 可以使用信号线和电阻开关层的组合来封盖电极并使其氧化最小化。 因此，存储元件中需要更少的层。 此外，原子层沉积允许更精确地控制电极厚度。 在一些实施例中，电极的厚度可以小于50埃。 总的来说，电极和电阻开关层的原子层沉积导致整个存储元件的较小厚度，使得它们更适合于高级节点的低纵横比特征。

    Method for forming metal oxides and silicides in a memory device
    8.
    发明授权
    Method for forming metal oxides and silicides in a memory device 有权
    在存储器件中形成金属氧化物和硅化物的方法

    公开(公告)号：US08975114B2

    公开(公告)日：2015-03-10

    申请号：US13804318

    申请日：2013-03-14

    Applicant: Intermolecular Inc. ,  Kabushiki Kaisha Toshiba ,  SanDisk 3D LLC

    Inventor： Dipankar Pramanik ,  Tony P. Chiang ,  Tim Minvielle ,  Takeshi Yamaguchi

    IPC: H01L21/00 ,  H01L21/16 ,  H01L45/00 ,  H01L27/10 ,  H01L27/24

    CPC classification number: H01L45/1253 ,  H01L27/101 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/16 ,  H01L45/1608

    Abstract: Embodiments of the invention generally relate to memory devices and methods for fabricating such memory devices. In one embodiment, a method for fabricating a resistive switching memory device includes depositing a metallic layer on a lower electrode disposed on a substrate and exposing the metallic layer to an activated oxygen source while heating the substrate to an oxidizing temperature within a range from about 300° C. to about 600° C. and forming a metal oxide layer from an upper portion of the metallic layer during an oxidation process. The lower electrode contains a silicon material and the metallic layer contains hafnium or zirconium. Subsequent to the oxidation process, the method further includes heating the substrate to an annealing temperature within a range from greater than 600° C. to about 850° C. while forming a metal silicide layer from a lower portion of the metallic layer during a silicidation process.

    Abstract translation: 本发明的实施例一般涉及用于制造这种存储器件的存储器件和方法。 在一个实施例中，一种用于制造电阻式开关存储器件的方法包括在设置在衬底上的下电极上沉积金属层，并将该金属层暴露于活性氧源，同时将衬底加热到​​约300的范围内的氧化温度 约600℃，并且在氧化过程中从金属层的上部形成金属氧化物层。 下部电极含有硅材料，金属层含有铪或锆。 在氧化处理之后，该方法还包括将衬底加热至大于600℃至约850℃的范围内的退火温度，同时在硅化期间从金属层的下部形成金属硅化物层 处理。

    Atomic Layer Deposition of Metal Oxide Materials for Memory Applications
    9.
    发明申请
    Atomic Layer Deposition of Metal Oxide Materials for Memory Applications 有权
    用于存储器应用的金属氧化物材料的原子层沉积

    公开(公告)号：US20150056749A1

    公开(公告)日：2015-02-26

    申请号：US14506298

    申请日：2014-10-03

    Applicant: Intermolecular Inc. ,  Kabushiki Kaisha Toshiba ,  SanDisk 3D LLC

    Inventor： Yun Wang ,  Tony P. Chiang ,  Vidyut Gopal ,  Imran Hashim ,  Dipankar Pramanik

    IPC: H01L45/00 ,  H01L21/02

    CPC classification number: H01L45/145 ,  C23C16/40 ,  C23C16/45525 ,  H01L21/02175 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02186 ,  H01L21/02189 ,  H01L21/02192 ,  H01L21/02194 ,  H01L21/022 ,  H01L21/0228 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/1266 ,  H01L45/146 ,  H01L45/1608 ,  H01L45/1616

    Abstract: Embodiments of the invention generally relate to nonvolatile memory devices, such as a ReRAM cells, and methods for manufacturing such memory devices, which includes optimized, atomic layer deposition (ALD) processes for forming metal oxide film stacks. The metal oxide film stacks contain a metal oxide coupling layer disposed on a metal oxide host layer, each layer having different grain structures/sizes. The interface disposed between the metal oxide layers facilitates oxygen vacancy movement. In many examples, the interface is a misaligned grain interface containing numerous grain boundaries extending parallel to the electrode interfaces, in contrast to the grains in the bulk film extending perpendicular to the electrode interfaces. As a result, oxygen vacancies are trapped and released during switching without significant loss of vacancies. Therefore, the metal oxide film stacks have improved switching performance and reliability during memory cell applications compared to traditional hafnium oxide based stacks of previous memory cells.

    Abstract translation: 本发明的实施例一般涉及非易失性存储器件，例如ReRAM单元，以及用于制造这种存储器件的方法，其包括用于形成金属氧化物膜堆叠的优化的原子层沉积（ALD）工艺。 金属氧化物膜堆叠包含设置在金属氧化物主体层上的金属氧化物耦合层，每个层具有不同的晶粒结构/尺寸。 设置在金属氧化物层之间的界面有助于氧空位移动。 在许多示例中，与垂直于电极界面延伸的体膜中的晶粒相反，界面是不对齐的晶粒界面，其包含平行于电极界面延伸的许多晶界。 因此，氧空缺在切换期间被捕获和释放，而空位明显损失。 因此，与以前的存储单元的传统的基于氧化铪的堆叠相比，金属氧化物膜堆叠在存储单元应用中具有改进的开关性能和可靠性。

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