公开(公告)号：US09917163B2

公开(公告)日：2018-03-13

申请号：US15437932

申请日：2017-02-21

Applicant: Infineon Technologies AG

Inventor： Andreas Meiser ,  Till Schloesser

IPC: H01L29/78 ,  H01L27/15 ,  H01L29/417 ,  H01L29/10 ,  H01L29/66 ,  H01L29/40

CPC classification number: H01L29/4175 ,  H01L21/2255 ,  H01L21/26586 ,  H01L27/156 ,  H01L29/063 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/1083 ,  H01L29/1087 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/408 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/66621 ,  H01L29/66636 ,  H01L29/66659 ,  H01L29/66696 ,  H01L29/66704 ,  H01L29/7825 ,  H01L29/7835

Abstract: A semiconductor device comprises a field effect transistor in a semiconductor substrate having a first main surface. The field effect transistor comprises a source region, a drain region, a body region, and a gate electrode at the body region. The gate electrode is configured to control a conductivity of a channel formed in the body region, and the gate electrode is disposed in gate trenches. The body region is disposed along a first direction between the source region and the drain region, the first direction being parallel to the first main surface. The body region has a shape of a ridge extending along the first direction, the body region being adjacent to the source region and the drain region. The semiconductor device further comprises a source contact and a body contact, the source contact being electrically connected to a source terminal, the body contact being electrically connected to the source contact and to the body region.

公开(公告)号：US09799762B2

公开(公告)日：2017-10-24

申请号：US13692059

申请日：2012-12-03

Applicant: Infineon Technologies AG

Inventor： Andreas Meiser ,  Till Schloesser

IPC: H01L29/78 ,  H01L29/40 ,  H01L29/66 ,  H01L29/417 ,  H01L29/08 ,  H01L29/10

CPC classification number: H01L29/7816 ,  H01L29/0856 ,  H01L29/0873 ,  H01L29/1095 ,  H01L29/404 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/66696 ,  H01L29/66704 ,  H01L29/7825

Abstract: A semiconductor device comprises a transistor formed in a semiconductor substrate having a first main surface. The transistor includes a source region, a drain region, a channel region, a drift zone, and a gate electrode being adjacent to the channel region. The gate electrode is configured to control a conductivity of a channel formed in the channel region, the channel region and the drift zone are disposed along a first direction between the source region and the drain region, the first direction being parallel to the first main surface. The channel region has a shape of a first ridge extending along the first direction, and the transistor includes a first field plate arranged adjacent to the drift zone.

公开(公告)号：US20160300944A1

公开(公告)日：2016-10-13

申请号：US15187889

申请日：2016-06-21

Applicant: Infineon Technologies AG

Inventor： Andreas Meiser ,  Till Schloesser ,  Franz Hirler

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/06 ,  H01L29/40 ,  H01L27/088 ,  H01L29/423 ,  H01L29/10

CPC classification number: H01L29/7813 ,  H01L27/088 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0865 ,  H01L29/0882 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/78 ,  H01L29/7811 ,  H01L29/7825 ,  H01L29/7835 ,  H01L29/7838 ,  H01L29/8083

Abstract: A semiconductor device includes a transistor formed in a semiconductor substrate having a main surface. The transistor includes a source region of a first conductivity type, a drain region of the first conductivity type, a channel region of a second conductivity type, a gate trench adjacent to a first sidewall of the channel region, a gate conductive material disposed in the gate trench, the gate conductive material being connected to a gate terminal, and a channel separation trench adjacent to a second sidewall of the channel region. The second sidewall faces the first sidewall via the channel region. The channel separation trench is filled with an insulating separation trench filling consisting of an insulating material in direct contact with the channel region. The source region and the drain region are disposed along a first direction. The first direction is parallel to the main surface.

Abstract translation: 半导体器件包括形成在具有主表面的半导体衬底中的晶体管。 晶体管包括第一导电类型的源极区域，第一导电类型的漏极区域，第二导电类型的沟道区域，与沟道区域的第一侧壁相邻的栅极沟槽，设置在该沟道区域中的栅极导电材料 栅极沟槽，栅极导电材料连接到栅极端子以及与沟道区域的第二侧壁相邻的沟道分离沟槽。 第二侧壁经由通道区域面向第一侧壁。 通道分离沟槽填充有由与沟道区直接接触的绝缘材料构成的绝缘分离沟槽填充物。 源极区域和漏极区域沿着第一方向设置。 第一个方向平行于主表面。

公开(公告)号：US09397092B2

公开(公告)日：2016-07-19

申请号：US14813738

申请日：2015-07-30

Applicant: Infineon Technologies AG

Inventor： Andreas Meiser ,  Markus Zundel ,  Till Schloesser

IPC: H01L27/08 ,  H01L49/02 ,  H01L21/768 ,  H01L29/40 ,  H01L27/06 ,  H01L21/00

CPC classification number: H01L27/0805 ,  H01L21/7687 ,  H01L21/76877 ,  H01L27/0629 ,  H01L28/40 ,  H01L28/60 ,  H01L28/90 ,  H01L29/407

Abstract: A semiconductor device in a semiconductor substrate includes a trench in a first main surface of the semiconductor substrate. The trench includes a first trench portion extending in a first direction and a second trench portion extending in the first direction. The first trench portion is connected with the second trench portion in a lateral direction. The first trench portion and the second trench portion are arranged one after the other along the first direction. The semiconductor device further includes a trench conductive structure having a conductive material disposed in the first trench portion, and a trench capacitor structure having a capacitor dielectric and a first capacitor electrode disposed in the second trench portion. The first capacitor electrode includes a layer lining a sidewall of the second trench portion.

Abstract translation: 半导体衬底中的半导体器件包括在半导体衬底的第一主表面中的沟槽。 沟槽包括沿第一方向延伸的第一沟槽部分和沿第一方向延伸的第二沟槽部分。 第一沟槽部分沿横向方向与第二沟槽部分连接。 第一沟槽部分和第二沟槽部分沿着第一方向一个接一个布置。 半导体器件还包括具有设置在第一沟槽部分中的导电材料的沟槽导电结构，以及具有电容器电介质的沟槽电容器结构和设置在第二沟槽部分中的第一电容器电极。 第一电容器电极包括衬在第二沟槽部分的侧壁上的层。

公开(公告)号：US09162868B2

公开(公告)日：2015-10-20

申请号：US14091492

申请日：2013-11-27

Applicant: Infineon Technologies AG

Inventor： Stefan Kolb ,  Andreas Meiser ,  Till Schloesser ,  Wolfgang Werner

IPC: H01L21/00 ,  B81B3/00 ,  G01P15/125 ,  G01N27/22 ,  G01L9/12 ,  B81C1/00

CPC classification number: B81B3/0021 ,  B81B3/0086 ,  B81B2201/0207 ,  B81B2201/0235 ,  B81B2201/0264 ,  B81B2201/0292 ,  B81B2203/0118 ,  B81B2203/0307 ,  B81B2203/04 ,  B81C1/0015 ,  G01H1/00 ,  G01H11/06 ,  G01L9/0072 ,  G01L9/12 ,  G01N27/223 ,  G01P15/125

Abstract: A MEMS device includes a fixed electrode and a movable electrode arranged isolated and spaced from the fixed electrode by a distance. The movable electrode is suspended against the fixed electrode by one or more spacers including an insulating material, wherein the movable electrode is laterally affixed to the one or more spacers.

Abstract translation: MEMS器件包括固定电极和可移动​​电极，与固定电极隔离并间隔一定距离。 可移动电极通过一个或多个包括绝缘材料的间隔件悬置在固定电极上，其中可动电极横向地固定到一个或多个间隔件上。

公开(公告)号：US11217658B2

公开(公告)日：2022-01-04

申请号：US16423535

申请日：2019-05-28

Applicant: Infineon Technologies AG

Inventor： Andreas Meiser ,  Grzegorz Kozlowski ,  Till Schloesser

IPC: H01L49/02 ,  H01L21/761 ,  H01L21/762

Abstract: The disclosure relates to a semiconductor device, including a semiconductor substrate of a first conductivity type and a semiconductor layer of a second conductivity type on the semiconductor substrate, the second conductivity type being different than the first conductivity type. The semiconductor device also includes an isolation structure electrically isolating a first region of the semiconductor layer from a second region of the semiconductor layer. A shallow trench isolation structure vertically extends from a surface of the semiconductor layer into the first region of the semiconductor layer. An electrical resistor is formed on the shallow trench isolation structure.

公开(公告)号：US10355087B2

公开(公告)日：2019-07-16

申请号：US15062370

申请日：2016-03-07

Applicant: Infineon Technologies AG

Inventor： Martin Vielemeyer ,  Andreas Meiser ,  Till Schloesser ,  Franz Hirler ,  Martin Poelzl

IPC: H01L29/10 ,  H01L29/78 ,  H01L29/66 ,  H01L21/28 ,  H01L29/40 ,  H01L29/417 ,  H01L29/423 ,  H01L21/265

Abstract: A semiconductor device includes a transistor in a semiconductor substrate having a main surface. The transistor includes a source region, a drain region, a channel region, a drift zone, a gate electrode, and a gate dielectric adjacent to the gate electrode. The gate electrode is disposed adjacent to at least two sides of the channel region. The channel region and the drift zone are disposed along a first direction parallel to the main surface between the source region and the drain region. The gate dielectric has a thickness that varies at different positions of the gate electrode.

公开(公告)号：US10246325B2

公开(公告)日：2019-04-02

申请号：US14832001

申请日：2015-08-21

Applicant: Infineon Technologies AG

Inventor： Stefan Kolb ,  Andreas Meiser ,  Till Schloesser ,  Wolfgang Werner

IPC: B81B3/00 ,  B81C1/00 ,  H01L21/00

Abstract: A method for producing a MEMS device comprises forming a semiconductor layer stack, the semiconductor layer stack comprising at least a first monocrystalline semiconductor layer, a second monocrystalline semiconductor layer and a third monocrystalline semiconductor layer, the second monocrystalline semiconductor layer formed between the first and third monocrystalline semiconductor layers. A semiconductor material of the second monocrystalline semiconductor layer is different from semiconductor materials of the first and third monocrystalline semiconductor layers. After forming the semiconductor layer stack, at least a portion of each of the first and third monocrystalline semiconductor layers is concurrently etched.

公开(公告)号：US09941403B2

公开(公告)日：2018-04-10

申请号：US13627215

申请日：2012-09-26

Applicant: Infineon Technologies AG

Inventor： Till Schloesser ,  Markus Zundel

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/40 ,  H01L29/423 ,  H01L27/088 ,  H01L29/06 ,  H01L21/8234

CPC classification number: H01L29/7813 ,  H01L21/823412 ,  H01L21/823481 ,  H01L21/823487 ,  H01L27/0883 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/66734 ,  H01L29/7803 ,  H01L29/7809 ,  H01L29/7828

Abstract: A semiconductor device includes a transistor including a source region, a drain region, and a gate electrode. The gate electrode is disposed in a first trench arranged in a top surface of the semiconductor substrate. The device further includes a control electrode. The control electrode is disposed in a second trench arranged in the top surface of the semiconductor substrate. The second trench has a second shape that is different from a first shape of the first trench.

公开(公告)号：US09748378B2

公开(公告)日：2017-08-29

申请号：US14656041

申请日：2015-03-12

Applicant: Infineon Technologies AG

Inventor： Karoline Koepp ,  Andreas Meiser ,  Till Schloesser

IPC: H01L27/088 ,  H01L29/78 ,  H01L29/40 ,  H01L29/423 ,  H01L29/66 ,  H01L29/06

CPC classification number: H01L29/7825 ,  H01L21/823456 ,  H01L21/823481 ,  H01L21/823487 ,  H01L27/088 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/66681 ,  H01L29/7813 ,  H01L29/7823 ,  H01L29/7835

Abstract: A semiconductor device includes a transistor in a semiconductor substrate having a first main surface. The transistor includes a source region, a drain region, a channel region, a drift zone, and a gate electrode adjacent to at least two sides of the channel region. The gate electrode is disposed in trenches extending in a first direction parallel to the first main surface. The gate electrode is electrically coupled to a gate terminal. The channel region and the drift zone are disposed along the first direction between the source region and the drain region. The semiconductor device further includes a conductive layer beneath the gate electrode and insulated from the gate electrode. The conductive layer is electrically connected to the gate terminal.