公开(公告)号：US20250036591A1

公开(公告)日：2025-01-30

申请号：US18912321

申请日：2024-10-10

Applicant: Intel Corporation

Inventor： Ilya K. Ganusov ,  Ashish Gupta ,  Chee Hak Teh ,  Sean R. Atsatt ,  Scott Jeremy Weber ,  Parivallal Kannan ,  Aman Gupta ,  Gary Brian Wallichs

IPC: G06F15/78 ,  H04L45/60 ,  H04L49/109

Abstract: Systems and methods described herein may relate to data transactions involving a microsector architecture. Control circuitry may organize transactions to and from the microsector architecture to, for example, enable direct addressing transactions as well as batch transactions across multiple microsectors. A data path disposed between programmable logic circuitry of a column of microsectors and a column of row controllers may form a micro-network-on-chip used by a network-on-chip to interface with the programmable logic circuitry.

公开(公告)号：US12197357B2

公开(公告)日：2025-01-14

申请号：US17556853

申请日：2021-12-20

Applicant: Intel Corporation

Inventor： Robert J. Safranek ,  Robert G. Blankenship ,  Venkatraman Iyer ,  Jeff Willey ,  Robert Beers ,  Darren S. Jue ,  Arvind A. Kumar ,  Debendra Das Sharma ,  Jeffrey C. Swanson ,  Bahaa Fahim ,  Vedaraman Geetha ,  Aaron T. Spink ,  Fulvio Spagna ,  Rahul R. Shah ,  Sitaraman V. Iyer ,  William Harry Nale ,  Abhishek Das ,  Simon P. Johnson ,  Yuvraj S. Dhillon ,  Yen-Cheng Liu ,  Raj K. Ramanujan ,  Robert A. Maddox ,  Herbert H. Hum ,  Ashish Gupta

IPC: G06F13/22 ,  G06F1/3287 ,  G06F8/71 ,  G06F8/77 ,  G06F9/30 ,  G06F9/445 ,  G06F9/46 ,  G06F11/10 ,  G06F12/0806 ,  G06F12/0808 ,  G06F12/0813 ,  G06F12/0815 ,  G06F12/0831 ,  G06F13/40 ,  G06F13/42 ,  H04L9/06 ,  H04L49/15 ,  G06F8/73 ,  H04L12/46 ,  H04L45/74

Abstract: A physical layer (PHY) is coupled to a serial, differential link that is to include a number of lanes. The PHY includes a transmitter and a receiver to be coupled to each lane of the number of lanes. The transmitter coupled to each lane is configured to embed a clock with data to be transmitted over the lane, and the PHY periodically issues a blocking link state (BLS) request to cause an agent to enter a BLS to hold off link layer flit transmission for a duration. The PHY utilizes the serial, differential link during the duration for a PHY associated task selected from a group including an in-band reset, an entry into low power state, and an entry into partial width state.

公开(公告)号：US12164462B2

公开(公告)日：2024-12-10

申请号：US17132663

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Ilya K. Ganusov ,  Ashish Gupta ,  Chee Hak Teh ,  Sean R. Atsatt ,  Scott Jeremy Weber ,  Parivallal Kannan ,  Aman Gupta ,  Gary Brian Wallichs

IPC: G06F15/78 ,  H04L45/60 ,  H04L49/109

Abstract: Systems and methods described herein may relate to data transactions involving a microsector architecture. Control circuitry may organize transactions to and from the microsector architecture to, for example, enable direct addressing transactions as well as batch transactions across multiple microsectors. A data path disposed between programmable logic circuitry of a column of microsectors and a column of row controllers may form a micro-network-on-chip used by a network-on-chip to interface with the programmable logic circuitry.

公开(公告)号：US20240031308A1

公开(公告)日：2024-01-25

申请号：US18478755

申请日：2023-09-29

Applicant: Intel Corporation

Inventor： Rahul Pal ,  Ashish Gupta ,  Keong Hong Oh ,  Gia Thuyet Ngo ,  Vikrant Kapila ,  Ankita Roy

IPC: H04L49/109

CPC classification number: H04L49/109

Abstract: An integrated circuit includes a core region of logic circuits and a network routed outside the core region. The network includes a wide layer and a narrow layer. The wide layer comprises first routers coupled in series. The narrow layer comprises second routers coupled in series.

公开(公告)号：US20240012772A1

公开(公告)日：2024-01-11

申请号：US18347236

申请日：2023-07-05

Applicant: Intel Corporation

Inventor： Robert J. Safranek ,  Robert G. Blankenship ,  Venkatraman Iyer ,  Jeff Willey ,  Robert Beers ,  Darren S. Jue ,  Arvind A. Kumar ,  Debendra Das Sharma ,  Jeffrey C. Swanson ,  Bahaa Fahim ,  Vedaraman Geetha ,  Aaron T. Spink ,  Fulvio Spagna ,  Rahul R. Shah ,  Sitaraman V. Iyer ,  William Harry Nale ,  Abhishek Das ,  Simon P. Johnson ,  Yuvraj S. Dhillon ,  Yen-Cheng Liu ,  Raj K. Ramanujan ,  Robert A. Maddox ,  Herbert H. Hum ,  Ashish Gupta

IPC: G06F13/22 ,  H04L49/15 ,  G06F12/0813 ,  G06F12/0815 ,  G06F12/0831 ,  G06F13/42 ,  G06F8/71 ,  G06F8/77 ,  G06F9/30 ,  G06F12/0806 ,  G06F9/46 ,  G06F13/40 ,  G06F9/445 ,  G06F1/3287 ,  G06F11/10 ,  H04L9/06 ,  G06F12/0808

CPC classification number: G06F13/22 ,  H04L49/15 ,  G06F12/0813 ,  G06F12/0815 ,  G06F12/0831 ,  G06F13/4286 ,  G06F8/71 ,  G06F8/77 ,  G06F9/30145 ,  G06F13/4221 ,  G06F12/0806 ,  G06F12/0833 ,  G06F9/466 ,  G06F13/4022 ,  G06F9/44505 ,  G06F13/4282 ,  G06F1/3287 ,  G06F13/4068 ,  G06F11/1004 ,  G06F13/4291 ,  H04L9/0662 ,  G06F12/0808 ,  H04L45/74

Abstract: A physical layer (PHY) is coupled to a serial, differential link that is to include a number of lanes. The PHY includes a transmitter and a receiver to be coupled to each lane of the number of lanes. The transmitter coupled to each lane is configured to embed a clock with data to be transmitted over the lane, and the PHY periodically issues a blocking link state (BLS) request to cause an agent to enter a BLS to hold off link layer flit transmission for a duration. The PHY utilizes the serial, differential link during the duration for a PHY associated task selected from a group including an in-band reset, an entry into low power state, and an entry into partial width state.

公开(公告)号：US20230031457A1

公开(公告)日：2023-02-02

申请号：US17957436

申请日：2022-09-30

Applicant: Intel Corporation

Inventor： Phil Geng ,  Ralph Miele ,  Christopher Gonzalez ,  Timothy Gates ,  Sanjoy Saha ,  Ashish Gupta ,  Sandeep Ahuja

IPC: B21C37/16

Abstract: Methods, systems, apparatus, and articles of manufacture to crimp a tube are disclosed. An example crimp disclosed herein includes a first crimp section extending between a first end of the crimp and a point along the crimp between the first end and a second end, a first inner diameter of the first crimp section constant between the first end and the point, and a second crimp section adjacent the first crimp section, the second crimp section extending between the point and the second end, a second inner diameter of the second crimp section to increase from the point to the second end.

公开(公告)号：US09626321B2

公开(公告)日：2017-04-18

申请号：US14060191

申请日：2013-10-22

Applicant: Intel Corporation

Inventor： Robert J. Safranek ,  Robert G. Blankenship ,  Venkatraman Iyer ,  Jeff Willey ,  Robert Beers ,  Darren S. Jue ,  Arvind A. Kumar ,  Debendra Das Sharma ,  Jeffrey C. Swanson ,  Bahaa Fahim ,  Vedaraman Geetha ,  Aaron T. Spink ,  Fulvio Spagna ,  Rahul R. Shah ,  Sitaraman V. Iyer ,  William Harry Nale ,  Abhishek Das ,  Simon P. Johnson ,  Yuvraj S. Dhillon ,  Yen-Cheng Liu ,  Raj K. Ramanujan ,  Robert A. Maddox ,  Herbert H. Hum ,  Ashish Gupta

IPC: G06F13/40 ,  G06F12/0831 ,  G06F13/42 ,  G06F9/30 ,  G06F12/0806 ,  H04L12/933 ,  G06F9/46 ,  G06F12/0813 ,  G06F12/0815 ,  H04L12/741 ,  G06F9/44

CPC classification number: G06F13/22 ,  G06F1/3287 ,  G06F8/71 ,  G06F8/73 ,  G06F8/77 ,  G06F9/30145 ,  G06F9/44505 ,  G06F9/466 ,  G06F11/1004 ,  G06F12/0806 ,  G06F12/0808 ,  G06F12/0813 ,  G06F12/0815 ,  G06F12/0831 ,  G06F12/0833 ,  G06F13/4022 ,  G06F13/4068 ,  G06F13/4221 ,  G06F13/4282 ,  G06F13/4286 ,  G06F13/4291 ,  G06F2212/1016 ,  G06F2212/2542 ,  G06F2212/622 ,  H04L9/0662 ,  H04L12/4641 ,  H04L45/74 ,  H04L49/15 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151 ,  Y02D10/40 ,  Y02D10/44 ,  Y02D30/30

Abstract: A physical layer (PHY) is coupled to a serial, differential link that is to include a number of lanes. The PHY includes a transmitter and a receiver to be coupled to each lane of the number of lanes. The transmitter coupled to each lane is configured to embed a clock with data to be transmitted over the lane, and the PHY periodically issues a blocking link state (BLS) request to cause an agent to enter a BLS to hold off link layer flit transmission for a duration. The PHY utilizes the serial, differential link during the duration for a PHY associated task selected from a group including an in-band reset, an entry into low power state, and an entry into partial width state

公开(公告)号：US09448278B2

公开(公告)日：2016-09-20

申请号：US14746764

申请日：2015-06-22

Applicant: INTEL CORPORATION

Inventor： Christopher R. Schroeder ,  Christopher W. Ackerman ,  James C. Shipley ,  Tolga Acikalin ,  Ioan Sauciuc ,  Michael L. Rutigliano ,  James G. Maveety ,  Ashish Gupta

IPC: G01R31/28 ,  G01R31/26 ,  G06F1/20 ,  H01L23/473 ,  H01L23/467 ,  F28F3/12

CPC classification number: G01R31/2875 ,  F28F3/12 ,  G01R31/2642 ,  G06F1/20 ,  G06F2200/201 ,  H01L23/467 ,  H01L23/473 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An apparatus to test a semiconductive device includes a base plane that holds at least one heat-transfer fluid unit cell. The at least one heat-transfer fluid unit cell includes a fluid supply structure including a supply-orifice cross section as well as a fluid return structure including a return-orifice cross section. The supply-orifice cross section is greater than the return-orifice cross section. A die interface is also included to be a liquid-impermeable material.

Abstract translation: 测试半导体装置的装置包括保持至少一个传热流体单元的基座。 至少一个传热流体单元包括包括供给孔横截面的流体供应结构以及包括回流孔横截面的流体返回结构。 供应孔横截面大于回流孔横截面。 模具界面也被包括为液体不可渗透的材料。

公开(公告)号：US12189550B2

公开(公告)日：2025-01-07

申请号：US18347236

申请日：2023-07-05

Applicant: Intel Corporation

Inventor： Robert J. Safranek ,  Robert G. Blankenship ,  Venkatraman Iyer ,  Jeff Willey ,  Robert Beers ,  Darren S. Jue ,  Arvind A. Kumar ,  Debendra Das Sharma ,  Jeffrey C. Swanson ,  Bahaa Fahim ,  Vedaraman Geetha ,  Aaron T. Spink ,  Fulvio Spagna ,  Rahul R. Shah ,  Sitaraman V. Iyer ,  William Harry Nale ,  Abhishek Das ,  Simon P. Johnson ,  Yuvraj S. Dhillon ,  Yen-Cheng Liu ,  Raj K. Ramanujan ,  Robert A. Maddox ,  Herbert H. Hum ,  Ashish Gupta

IPC: G06F13/22 ,  G06F1/3287 ,  G06F8/71 ,  G06F8/77 ,  G06F9/30 ,  G06F9/445 ,  G06F9/46 ,  G06F11/10 ,  G06F12/0806 ,  G06F12/0808 ,  G06F12/0813 ,  G06F12/0815 ,  G06F12/0831 ,  G06F13/40 ,  G06F13/42 ,  H04L9/06 ,  H04L49/15 ,  G06F8/73 ,  H04L12/46 ,  H04L45/74

Abstract: A physical layer (PHY) is coupled to a serial, differential link that is to include a number of lanes. The PHY includes a transmitter and a receiver to be coupled to each lane of the number of lanes. The transmitter coupled to each lane is configured to embed a clock with data to be transmitted over the lane, and the PHY periodically issues a blocking link state (BLS) request to cause an agent to enter a BLS to hold off link layer flit transmission for a duration. The PHY utilizes the serial, differential link during the duration for a PHY associated task selected from a group including an in-band reset, an entry into low power state, and an entry into partial width state.

公开(公告)号：US10248591B2

公开(公告)日：2019-04-02

申请号：US15393153

申请日：2016-12-28

Applicant: Intel Corporation

Inventor： Robert J. Safranek ,  Robert G. Blankenship ,  Venkatraman Iyer ,  Jeff Willey ,  Robert H. Beers ,  Darren S. Jue ,  Arvind A. Kumar ,  Debendra Das Sharma ,  Jeffrey C. Swanson ,  Bahaa Fahim ,  Vedaraman Geetha ,  Aaron T. Spink ,  Fulvio Spagna ,  Rahul R. Shah ,  Sitaraman V. Iyer ,  William Harry Nale ,  Abhishek Das ,  Simon P. Johnson ,  Yuvraj S. Dhillon ,  Yen-Cheng Liu ,  Raj K. Ramanujan ,  Robert A. Maddox ,  Herbert H. Hum ,  Ashish Gupta

IPC: G06F13/22 ,  G06F12/0831 ,  G06F13/42 ,  G06F8/71 ,  G06F8/77 ,  G06F9/30 ,  G06F12/0806 ,  H04L12/933 ,  G06F9/46 ,  G06F13/40 ,  G06F12/0813 ,  G06F12/0815 ,  G06F9/445 ,  G06F1/3287 ,  G06F11/10 ,  H04L9/06 ,  G06F12/0808 ,  H04L12/741 ,  G06F8/73 ,  H04L12/46

Abstract: A physical layer (PHY) is coupled to a serial, differential link that is to include a number of lanes. The PHY includes a transmitter and a receiver to be coupled to each lane of the number of lanes. The transmitter coupled to each lane is configured to embed a clock with data to be transmitted over the lane, and the PHY periodically issues a blocking link state (BLS) request to cause an agent to enter a BLS to hold off link layer flit transmission for a duration. The PHY utilizes the serial, differential link during the duration for a PHY associated task selected from a group including an in-band reset, an entry into low power state, and an entry into partial width state.