公开(公告)号：US20230420400A1

公开(公告)日：2023-12-28

申请号：US18244689

申请日：2023-09-11

Applicant: Intel Corporation

Inventor： Pramod MALATKAR ,  Weng Hong TEH ,  John S. GUZEK ,  Robert L. SANKMAN

IPC: H01L23/00 ,  H01L27/08 ,  H01L23/48 ,  H01L23/538

CPC classification number: H01L24/09 ,  H01L27/08 ,  H01L24/19 ,  H01L24/97 ,  H01L23/481 ,  H01L23/5384 ,  H01L23/5386 ,  H01L23/552

Abstract: A packaged semiconductor die with a bumpless die-package interface and methods of fabrication are described. For example, a semiconductor package includes a substrate having a land side with a lowermost layer of conductive vias. A semiconductor die is embedded in the substrate and has an uppermost layer of conductive lines, one of which is coupled directly to a conductive via of the lowermost layer of conductive vias of the substrate. In another example, a semiconductor package includes a substrate having a land side with a lowermost layer of conductive vias. A semiconductor die is embedded in the substrate and has an uppermost layer of conductive lines with a layer of conductive vias disposed thereon. At least one of the conductive lines is coupled directly to a conductive via of the semiconductor die which is coupled directly to a conductive via of the lowermost layer of conductive vias of the substrate.

公开(公告)号：US20250062168A1

公开(公告)日：2025-02-20

申请号：US18451852

申请日：2023-08-18

Applicant: Intel Corporation

Inventor： Justin WHETTEN ,  Zhou YANG ,  Zheng KANG ,  Haowen LIU ,  Bassam ZIADEH ,  Vijay Krishnan SUBRAMANIAN ,  John HARPER ,  Pramod MALATKAR ,  Patrick NARDI ,  Anthony MONTERROSA ,  Michael TAN ,  Sean BUSHELL

IPC: H01L23/24 ,  B23K26/362 ,  H01L21/268 ,  H01L21/67

Abstract: The present disclosure is directed to a patterned stiffener that includes a metallic body, which is a component of and is attached to a semiconductor device platform for providing rigidity. In an aspect, there are patterned sections formed on the metallic body that act to modulate the metallic body to obtain a desired configuration for the semiconductor device platform. In another aspect, the present disclosure is also directed to a method that includes providing a platform for forming an electronic component, disposing a stiffener having a metallic body on the platform, disposing at least one semiconductor device onto the platform, performing one or more bonding process steps, and exposing the stiffener to localized heating to modulate changes in the stiffener to a pre-determined shape or desired configuration.

公开(公告)号：US20180047702A1

公开(公告)日：2018-02-15

申请号：US15791292

申请日：2017-10-23

Applicant: Intel Corporation

Inventor： Pramod MALATKAR

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L23/522 ,  H01L41/083 ,  H01L21/56 ,  H01L25/065 ,  H01L25/07 ,  H01L25/11 ,  H01L23/29 ,  H01L23/538

CPC classification number: H01L24/83 ,  H01L21/568 ,  H01L23/29 ,  H01L23/3135 ,  H01L23/3142 ,  H01L23/481 ,  H01L23/5226 ,  H01L23/538 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L25/0657 ,  H01L25/074 ,  H01L25/117 ,  H01L41/083 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/12105 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16148 ,  H01L2224/16225 ,  H01L2224/24105 ,  H01L2224/24226 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73209 ,  H01L2224/73259 ,  H01L2224/80001 ,  H01L2224/83951 ,  H01L2224/92224 ,  H01L2225/06503 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06544 ,  H01L2225/06568 ,  H01L2225/06586 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/18161 ,  H01L2924/00

Abstract: The present disclosure relates to the field of integrated circuit package design and, more particularly, to packages using a bumpless build-up layer (BBUL) designs. Embodiments of the present description relate to the field of fabricating microelectronic packages, wherein a first microelectronic device having through-silicon vias may be stacked with a second microelectronic device and used in a bumpless build-up layer package.

公开(公告)号：US20170268971A1

公开(公告)日：2017-09-21

申请号：US15075086

申请日：2016-03-18

Applicant: Intel Corporation

Inventor： Ravindranth V. MAHAJAN ,  Rajendra C. DIAS ,  Pramod MALATKAR ,  Steven A. KLEIN ,  Vijay SUBRAMANIA ,  Aleksandar ALEKSOV ,  Robert L. SANKMAN

IPC: G01N3/08

CPC classification number: G01N3/08 ,  G01N2203/0085 ,  G01N2203/0282

Abstract: Embodiments are generally directed to membrane test for mechanical testing of wearable devices. A mechanical testing system includes an actuation mechanism including a clamp to hold a membrane including stretchable electronics over an opening in the actuation mechanism, wherein the actuation mechanism is to apply pressure to the membrane through the opening; and a testing logic to control the application and release of pressure on the membrane by the actuation mechanism.

公开(公告)号：US20250105119A1

公开(公告)日：2025-03-27

申请号：US18373848

申请日：2023-09-27

Applicant: Intel Corporation

Inventor： Yuqin LI ,  Jesse JONES ,  Sandrine LTEIF ,  Srinivas V. PIETAMBARAM ,  Suresh Tanaji NARUTE ,  Pramod MALATKAR ,  Gang DUAN ,  Khaled AHMED

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/00 ,  H01L23/15

Abstract: Embodiments disclosed herein include glass cores with vias that are lined by a self-healing liner. In an embodiment, an apparatus comprises a substrate that comprises a solid glass layer with an opening through a thickness of the substrate. In an embodiment, a liner is in contact with a sidewall of the opening, where the liner comprises a polymer matrix with capsules distributed through the polymer matrix. In an embodiment, each capsule comprises a shell, and a core within the shell. In an embodiment, the core comprises an organic material. In an embodiment, a via is in the opening and in contact with the liner, and the via is electrically conductive.

公开(公告)号：US20190043747A1

公开(公告)日：2019-02-07

申请号：US16075095

申请日：2016-04-02

Applicant: Intel Corporation

Inventor： Pramod MALATKAR ,  Richard J. HARRIES ,  Robert L. SANKMAN ,  David C. MCCOY

IPC: H01L21/683 ,  H01L23/31 ,  H01L23/48 ,  H01L23/538 ,  H01L21/56 ,  H01L23/00

Abstract: Techniques and mechanisms for providing flexible packaged circuit structures. In an embodiment, a flexible circuit device includes first and second conductive contacts and an interconnect that is coupled between such conductive contacts. While the flexible circuit device is in a baseline (“flat”) configuration, a first side of the flexible circuit device extends at least in part in a flat plane, and a portion of the interconnect includes a point that, with respect to a distance from the flat plane, is a maximum or a minimum of the interconnect. A mold compound of a flexible package encapsulates the portion of the interconnect. In another embodiment, a range spanned by the interconnect along a line orthogonal to the flat plane is at least two times an average height of the interconnect.

公开(公告)号：US20240162134A1

公开(公告)日：2024-05-16

申请号：US18418154

申请日：2024-01-19

Applicant: Intel Corporation

Inventor： Xiao LU ,  Jiongxin LU ,  Christopher COMBS ,  Alexander HUETTIS ,  John HARPER ,  Jieping ZHANG ,  Nachiket R. RARAVIKAR ,  Pramod MALATKAR ,  Steven A. KLEIN ,  Carl DEPPISCH ,  Mohit SOOD

IPC: H01L23/498 ,  B23K3/06 ,  H01L23/538

CPC classification number: H01L23/49833 ,  B23K3/0623 ,  H01L23/49822 ,  H01L23/4985 ,  H01L23/5387

Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises a first substrate; a second substrate; and an array of interconnects electrically coupling the first substrate to the second substrate. In an embodiment, the array of interconnects comprises first interconnects, wherein the first interconnects have a first volume and a first material composition, and second interconnects, wherein the second interconnects have a second volume and a second material composition, and wherein the first volume is different than the second volume and/or the first material composition is different than the second material composition.

公开(公告)号：US20190103345A1

公开(公告)日：2019-04-04

申请号：US15721707

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Kyle YAZZIE ,  Venkata Suresh R. GUTHIKONDA ,  Patrick NARDI ,  Santosh SANKARASUBRAMANIAN ,  Kevin Y. LIN ,  Leigh M. TRIBOLET ,  John L. HARPER ,  Pramod MALATKAR

IPC: H01L23/498 ,  H01L23/367 ,  H01L21/50 ,  H01L23/52 ,  H01L23/00 ,  H05K1/02

Abstract: An apparatus, comprising a first platform comprising a first working surface having a first non-planar portion; and a second platform comprising a second working surface having a second non-planar portion, wherein: the second working surface is opposite the first working surface, a distance between the first working surface and the second working surface is adjustable, the first non-planar portion comprises a first curved portion, and the second non-planar portion comprises a second curved portion opposite the first curved portion.

公开(公告)号：US20190043776A1

公开(公告)日：2019-02-07

申请号：US16074755

申请日：2016-04-02

Applicant: Intel Corporation

Inventor： Pramod MALATKAR ,  Aleksandar ALEKSOV ,  Dilan SENEVIRATNE ,  Edvin CETEGEN

IPC: H01L23/31 ,  H01L21/56 ,  H01L25/065

Abstract: Techniques and mechanisms for providing packaged circuitry. In an embodiment, first circuit structures are coupled to a release layer on a first side of a substrate, and second circuit structures are coupled to another release layer on a second side of the substrate. Respective portions of mold compound are variously injection molded or otherwise deposited around the first circuit structures and around the second circuit structures. The mold compound portions are cured while the first circuit structures and the second circuit structures are on opposite respective sides of the substrate. In another embodiment, the first circuit structures and the second circuit structures are separated from each other and from the substrate, after curing of the mold compound portions, to form distinct packaged devices.

公开(公告)号：US20170268972A1

公开(公告)日：2017-09-21

申请号：US15075090

申请日：2016-03-18

Applicant: Intel Corporation

Inventor： Vijay Krishnan SUBRAMANIAN ,  Steven A. KLEIN ,  Rajendra C. DIAS ,  Pramod MALATKAR ,  Aleksandar ALEKSOV ,  Ravindranath V. MAHAJAN ,  Robert L. SANKMAN

IPC: G01N3/08

CPC classification number: G01N3/08 ,  G01N2203/0085

Abstract: Embodiments are generally directed to a lateral expansion apparatus for mechanical testing of stretchable electronics. An embodiment of a system includes a compressible cylinder to apply mechanical forces to a stretchable electronics device by the compression and release of the compressible cylinder; a compression unit to compress to the compressible cylinder, wherein the compression unit is to apply a compression force in a direction along an axis of the compressible cylinder to generate lateral expansion of the compressible cylinder; and a testing logic to control compression and release of the compressible cylinder.