公开(公告)号：US09576904B2

公开(公告)日：2017-02-21

申请号：US14827763

申请日：2015-08-17

Applicant: Micron Technology, Inc.

Inventor： Gurtej S. Sandhu ,  Nishant Sinha ,  John A. Smythe

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/532 ,  H01L23/522 ,  H01L25/065 ,  H01L25/00 ,  H01L27/105

CPC classification number: H01L23/5283 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76877 ,  H01L21/76879 ,  H01L23/5226 ,  H01L23/53209 ,  H01L23/5329 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/105 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Semiconductor devices comprise at least one integrated circuit layer, at least one conductive trace and an insulative material adjacent at least a portion of the at least one conductive trace. At least one interconnect structure extends through a portion of the at least one conductive trace and a portion of the insulative material, the at least one interconnect structure comprising a transverse cross-sectional dimension through the at least one conductive trace which differs from a transverse cross-sectional dimension through the insulative material.

Abstract translation: 半导体器件包括至少一个集成电路层，至少一个导电迹线和与至少一个导电迹线的至少一部分相邻的绝缘材料。 至少一个互连结构延伸穿过所述至少一个导电迹线的一部分和所述绝缘材料的一部分，所述至少一个互连结构包括穿过所述至少一个导电迹线的横向截面尺寸，所述导电迹线与横向交叉不同 通过绝缘材料的尺寸。

公开(公告)号：US20140225028A1

公开(公告)日：2014-08-14

申请号：US14253005

申请日：2014-04-15

Applicant: Micron Technology, Inc.

Inventor： Nishant Sinha ,  J. Neil Greeley

IPC: C09K13/08 ,  C09K13/06

CPC classification number: C09K13/08 ,  C09K13/06 ,  H01L21/31055 ,  H01L21/31111

Abstract: Methods for preventing isotropic removal of materials at corners faulted by seams, keyholes, and other anomalies in films or other structures include use of etch blockers to cover or coat such corners. This covering or coating prevents exposure of the corners to isotropic etch solutions and cleaning solutions and, thus, prevents higher material removal rates at the corners than at smoother areas of the structure or film. Solutions, including wet etchants and cleaning solutions, that include at least one type of etch blocker are also disclosed, as are systems for preventing higher rates of material removal at corners formed by seams, crevices, or recesses in a film or other structure. Semiconductor device structures in which etch blockers are located so as to prevent isotropic etchants from removing material from corners of seams, crevices, or recesses of a film or other structure at undesirably high rates are also disclosed.

Abstract translation: 在膜或其他结构中的接缝，键孔和其它异常现象的角落处的材料的各向同性去除方法包括使用蚀刻阻挡剂来覆盖或涂覆这些角。 这种覆盖物或涂层防止角部暴露于各向同性蚀刻溶液和清洁溶液，并且因此防止在角部比在结构或膜的平滑区域更高的材料去除速率。 还公开了包括至少一种类型的蚀刻阻挡剂的解决方案，包括湿蚀刻剂和清洁溶液，以及用于防止在膜或其它结构中由接缝，缝隙或凹陷形成的拐角处更高速率的材料去除的系统。 还公开了其中蚀刻阻挡剂被定位以防止各向同性蚀刻剂从不期望的高速率的接缝，裂缝或膜或其它结构的凹陷的角落移除材料的半导体器件结构。

公开(公告)号：US20140175653A1

公开(公告)日：2014-06-26

申请号：US14191086

申请日：2014-02-26

Applicant: Micron Technology, Inc.

Inventor： Gurtej S. Sandhu ,  Nishant Sinha ,  John A. Smythe

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L23/5283 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76877 ,  H01L21/76879 ,  H01L23/5226 ,  H01L23/53209 ,  H01L23/5329 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/105 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Semiconductor devices comprise at least one integrated circuit layer, at least one conductive trace and an insulative material adjacent at least a portion of the at least one conductive trace. At least one interconnect structure extends through a portion of the at least one conductive trace and a portion of the insulative material, the at least one interconnect structure comprising a transverse cross-sectional dimension through the at least one conductive trace which differs from a transverse cross-sectional dimension through the insulative material.

Abstract translation: 半导体器件包括至少一个集成电路层，至少一个导电迹线和与至少一个导电迹线的至少一部分相邻的绝缘材料。 至少一个互连结构延伸穿过所述至少一个导电迹线的一部分和所述绝缘材料的一部分，所述至少一个互连结构包括穿过所述至少一个导电迹线的横向截面尺寸，所述导电迹线与横向交叉不同 通过绝缘材料的尺寸。

公开(公告)号：US20130175662A1

公开(公告)日：2013-07-11

申请号：US13784431

申请日：2013-03-04

Applicant: Micron Technology, Inc.

Inventor： Nishant Sinha ,  Gurtej S. Sandhu ,  John Smythe

IPC: H01L21/762

CPC classification number: H01L21/76254

Abstract: Electronic apparatus, systems, and methods include a semiconductor layer bonded to a bulk region of a wafer or a substrate, in which the semiconductor layer can be bonded to the bulk region using electromagnetic radiation. Additional apparatus, systems, and methods are disclosed.

Abstract translation: 电子设备，系统和方法包括结合到晶片或基板的主体区域的半导体层，其中半导体层可以使用电磁辐射结合到主体区域。 公开了附加装置，系统和方法。

公开(公告)号：US20180114901A1

公开(公告)日：2018-04-26

申请号：US15848399

申请日：2017-12-20

Applicant: Micron Technology, Inc.

Inventor： Sanh D. Tang ,  Scott E. Sills ,  Whitney L. West ,  Rob B. Goodwin ,  Nishant Sinha

IPC: H01L45/00 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L45/1266 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76858 ,  H01L21/76877 ,  H01L21/76882 ,  H01L21/76883 ,  H01L23/53247 ,  H01L23/53252 ,  H01L45/04 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/141 ,  H01L45/142 ,  H01L45/143 ,  H01L45/145 ,  H01L45/146 ,  H01L45/16 ,  H01L45/1608 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods of forming conductive elements, such as interconnects and electrodes, for semiconductor structures and memory cells. The methods include forming a first conductive material and a second conductive material comprising silver in a portion of at least one opening and performing a polishing process to fill the at least one opening with at least one of the first and second conductive materials. An annealing process may be performed to form a mixture or an alloy of the silver and the first conductive material. The methods enable formation of silver-containing conductive elements having reduced dimensions (e.g., less than about 20 nm). The resulting conductive elements have a desirable resistivity. The methods may be used, for example, to form interconnects for electrically connecting active devices and to form electrodes for memory cells. A semiconductor structure and a memory cell including such a conductive structure are also disclosed.

公开(公告)号：US09520558B2

公开(公告)日：2016-12-13

申请号：US13961479

申请日：2013-08-07

Applicant: Micron Technology, Inc.

Inventor： Sanh D. Tang ,  Scott E. Sills ,  Whitney L. West ,  Rob B. Goodwin ,  Nishant Sinha

IPC: H01L45/00 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L45/1266 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76858 ,  H01L21/76877 ,  H01L21/76882 ,  H01L21/76883 ,  H01L23/53247 ,  H01L23/53252 ,  H01L45/04 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/141 ,  H01L45/142 ,  H01L45/143 ,  H01L45/145 ,  H01L45/146 ,  H01L45/16 ,  H01L45/1608 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods of forming conductive elements, such as interconnects and electrodes, for semiconductor structures and memory cells. The methods include forming a first conductive material and a second conductive material comprising silver in a portion of at least one opening and performing a polishing process to fill the at least one opening with at least one of the first and second conductive materials. An annealing process may be performed to form a mixture or an alloy of the silver and the first conductive material. The methods enable formation of silver containing conductive elements having reduced dimensions (e.g., less than about 20 nm). The resulting conductive elements have a desirable resistivity. The methods may be used, for example, to form interconnects for electrically connecting active devices and to form electrodes for memory cells. A semiconductor structure and a memory cell including such a conductive structure are also disclosed.

Abstract translation: 形成用于半导体结构和存储单元的导电元件例如互连和电极的方法。 所述方法包括在至少一个开口的一部分中形成第一导电材料和第二导电材料，所述第二导电材料包括银，并且执行抛光工艺以用至少一个第一和第二导电材料填充所述至少一个开口。 可以进行退火处理以形成银和第一导电材料的混合物或合金。 该方法能够形成具有减小的尺寸（例如，小于约20nm）的含银导电元件。 所得的导电元件具有所需的电阻率。 所述方法可以用于例如形成用于电连接有源器件并形成用于存储器单元的电极的互连。 还公开了一种半导体结构和包括这种导电结构的存储单元。

公开(公告)号：US09431493B2

公开(公告)日：2016-08-30

申请号：US14875497

申请日：2015-10-05

Applicant: Micron Technology, Inc.

Inventor： Nishant Sinha

IPC: H01L29/423 ,  B82Y10/00 ,  H01L21/28 ,  H01L21/316 ,  H01L29/788 ,  H01L21/02 ,  H01L21/285 ,  H01L21/288

CPC classification number: H01L29/42332 ,  B82Y10/00 ,  H01L21/02068 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/2855 ,  H01L21/28556 ,  H01L21/288 ,  H01L21/316 ,  H01L29/7881

Abstract: Some embodiments include methods of forming charge-trapping zones. The methods may include forming nanoparticles, transferring the nanoparticles to a liquid to form a dispersion, forming an aerosol from the dispersion, and then directing the aerosol onto a substrate to form charge-trapping centers comprising the nanoparticles. The charge-trapping zones may be incorporated into flash memory cells.

公开(公告)号：US09159569B2

公开(公告)日：2015-10-13

申请号：US14019298

申请日：2013-09-05

Applicant: Micron Technology, Inc.

Inventor： Nishant Sinha

IPC: H01L21/28 ,  B82Y10/00 ,  H01L21/316 ,  H01L29/423 ,  H01L29/788

CPC classification number: H01L29/42332 ,  B82Y10/00 ,  H01L21/02068 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/2855 ,  H01L21/28556 ,  H01L21/288 ,  H01L21/316 ,  H01L29/7881

Abstract: Some embodiments include methods of forming charge-trapping zones. The methods may include forming nanoparticles, transferring the nanoparticles to a liquid to form a dispersion, forming an aerosol from the dispersion, and then directing the aerosol onto a substrate to form charge-trapping centers comprising the nanoparticles. The charge-trapping zones may be incorporated into flash memory cells.

Abstract translation: 一些实施方案包括形成电荷捕获区的方法。 所述方法可以包括形成纳米颗粒，将纳米颗粒转移到液体中以形成分散体，从分散体形成气溶胶，然后将气溶胶引导到基底上以形成包含纳米颗粒的电荷捕获中心。 电荷捕获区域可以并入闪存单元中。

公开(公告)号：US20140373880A1

公开(公告)日：2014-12-25

申请号：US14479440

申请日：2014-09-08

Applicant: Micron Technology, Inc.

Inventor： Nishant Sinha ,  Stephen J. Kramer ,  Gurtej S. Sandhu

IPC: H01L21/67 ,  B03C1/01

CPC classification number: H01L21/6704 ,  B03C1/01 ,  B03C2201/16 ,  B03C2201/20 ,  B08B3/10 ,  C11D3/1206 ,  C11D3/1213 ,  C11D7/20 ,  C11D17/0013 ,  H01L21/67028

Abstract: Methods and apparatus are provided for cleaning a substrate (e.g., wafer) in the fabrication of semiconductor devices utilizing a composition of magnetic particles dispersed within a base fluid to remove contaminants from a surface of the substrate.

Abstract translation: 提供的方法和装置用于在半导体器件的制造中清洗衬底（例如，晶片），该半导体器件利用分散在基础流体内的磁性颗粒的组合物从衬底的表面去除污染物。

公开(公告)号：US20140256098A1

公开(公告)日：2014-09-11

申请号：US14283291

申请日：2014-05-21

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Sanh D. Tang ,  John Zahurak ,  Siddartha Kondoju ,  Haitao Liu ,  Nishant Sinha

IPC: H01L27/112 ,  H01L27/115

CPC classification number: H01L27/11293 ,  H01L21/823885 ,  H01L27/0688 ,  H01L27/101 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/11206 ,  H01L27/11517 ,  H01L27/11524 ,  H01L27/11551 ,  H01L27/11563 ,  H01L27/11578 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7881 ,  H01L29/792

Abstract: Memories and their formation are disclosed. One such memory has a first array of first memory cells extending in a first direction from a first surface of a semiconductor. A second array of second memory cells extends in a second direction, opposite to the first direction, from a second surface of the semiconductor. Both arrays may be non-volatile memory arrays. For example, one of the memory arrays may be a NAND flash memory array, while the other may be a one-time-programmable memory array.

Abstract translation: 记忆及其形成被披露。 一个这样的存储器具有从半导体的第一表面沿第一方向延伸的第一存储单元阵列。 第二阵列的第二存储单元从与半导体的第二表面在第二方向相反的第二方向延伸。 两个阵列可以是非易失性存储器阵列。 例如，存储器阵列之一可以是NAND快闪存储器阵列，而另一个可以是一次可编程存储器阵列。