公开(公告)号：US5379230A

公开(公告)日：1995-01-03

申请号：US232402

申请日：1994-04-25

申请人： Masatoshi Morikawa ,  Isao Yoshida ,  Terumi Sawase ,  Kouzou Sakamoto ,  Takeaki Okabe

发明人： Masatoshi Morikawa ,  Isao Yoshida ,  Terumi Sawase ,  Kouzou Sakamoto ,  Takeaki Okabe

IPC分类号： G06F1/00 ,  G01Q70/00 ,  G05F1/56 ,  H01L21/822 ,  H01L27/04 ,  H03K17/08 ,  H03K17/082 ,  H03M1/08 ,  G01K7/00 ,  H03K17/12

CPC分类号： H03K17/18 ,  H03K17/0822 ,  H03K2017/0806

摘要： A semiconductor integrated circuit has a semiconductor output device (3) , a sensor (5) generating an electric signal (7) relevant to heat generation (6) of the output device (3) and a microprocessor unit MPU 2, inside a chip (1). The MPU (2) is constructed of a memory (20) and CPU (22). The electric signal (7) generated from the sensor (5) is processed by the CPU (22) in accordance with a stored program of the memory (20). Accordingly, the drivability of the semiconductor output device (3) can be set in an optimum state corresponding to changes in chip temperature including changes that are only momentary.

摘要翻译： 半导体集成电路具有半导体输出装置（3），产生与输出装置（3）的发热（6）有关的电信号（7）的传感器（5）和芯片内的微处理器单元MPU2 1）。 MPU（2）由存储器（20）和CPU（22）构成。 根据存储器（20）的存储程序，由CPU（22）处理从传感器（5）产生的电信号（7）。 因此，可以将半导体输出装置（3）的驾驶性能设定为对应于仅包含瞬时变化的芯片温度变化的最佳状态。

公开(公告)号：US4814288A

公开(公告)日：1989-03-21

申请号：US72164

申请日：1987-07-10

申请人： Masatoshi Kimura ,  Takeaki Okabe ,  Isao Yoshida ,  Kouzou Sakamoto ,  Kazuo Hoya ,  Kouichiro Satonaka ,  Toyomasa Koda ,  Shigeo Ohtaka

发明人： Masatoshi Kimura ,  Takeaki Okabe ,  Isao Yoshida ,  Kouzou Sakamoto ,  Kazuo Hoya ,  Kouichiro Satonaka ,  Toyomasa Koda ,  Shigeo Ohtaka

IPC分类号： H01L27/08 ,  H01L21/331 ,  H01L21/76 ,  H01L21/8222 ,  H01L21/8234 ,  H01L21/8248 ,  H01L21/8249 ,  H01L27/04 ,  H01L27/06 ,  H01L27/088 ,  H01L29/73 ,  H01L29/732 ,  H01L29/78 ,  H01L21/20 ,  H01L21/302

CPC分类号： H01L21/8249 ,  H01L27/0623

摘要： A method of fabricating semiconductor devices which include vertical elements and control elements. A well is formed by etching in a semiconductor substrate of a first conductivity type, and a first epitaxial layer having a second conductivity type opposite to the first conductivity type is epitaxially grown, followed by etching and/or grinding and/or polishing to fill said well. Further, a second epitaxial layer of the first conductivity type is epitaxially grown on the substrate and on the first epitaxial layer, and an impurity-doped layer of the second conductivity type for isolation is formed in the second epitaxial layer to penetrate therethrough. A first element is formed in the second epitaxial layer in a portion that corresponds to the well, and a second element having a vertical structure and having a current capability higher than that of the first element is formed except a portion of the second epitaxial layer that corresponds to the well.

摘要翻译： 一种制造包括垂直元件和控制元件的半导体器件的方法。 通过在第一导电类型的半导体衬底中蚀刻形成阱，并且外延生长具有与第一导电类型相反的第二导电类型的第一外延层，随后进行蚀刻和/或研磨和/或抛光以填充所述 好。 此外，第一导电类型的第二外延层在衬底和第一外延层上外延生长，并且在第二外延层中形成用于隔离的第二导电类型的杂质掺杂层以穿透其中。 在对应于阱的部分中的第二外延层中形成第一元件，并且除了第二外延层的一部分之外，形成具有比第一元件的电流能力高的垂直结构并具有电流能力的第二元件， 对应于井。

公开(公告)号：US4831424A

公开(公告)日：1989-05-16

申请号：US62388

申请日：1987-06-15

申请人： Isao Yoshida ,  Takeaki Okabe ,  Mitsuo Ito ,  Kazutoshi Ashikawa ,  Tetsuo Iijima

发明人： Isao Yoshida ,  Takeaki Okabe ,  Mitsuo Ito ,  Kazutoshi Ashikawa ,  Tetsuo Iijima

IPC分类号： H03F1/52 ,  H01L27/02 ,  H01L27/04 ,  H01L27/06 ,  H01L29/78 ,  H02H7/20 ,  H03F1/42

CPC分类号： H01L29/7808 ,  H01L27/0255 ,  H01L29/7811 ,  H01L29/0692 ,  H01L29/866 ,  H01L2924/0002

摘要： An insulated gate semiconductor device contains a protective element for protecting the gate electrode of an insulated gate field effect transistor. The protective element is formed of the same semiconductor layer as that of the gate electrode of the insulated gate field effect transistor and is formed integrally with the gate electrode on an insulating film formed on the surface of a semiconductor substrate.

摘要翻译： 绝缘栅半导体器件包含用于保护绝缘栅场效应晶体管的栅电极的保护元件。 保护元件由与绝缘栅场效应晶体管的栅电极相同的半导体层形成，并与形成在半导体基板的表面上的绝缘膜上的栅电极一体形成。

公开(公告)号：US4213140A

公开(公告)日：1980-07-15

申请号：US922371

申请日：1978-07-06

申请人： Takeaki Okabe ,  Isao Yoshida ,  Mineo Katsueda ,  Hidefumi Ito ,  Masatomo Furumi ,  Shikayuki Ochi

发明人： Takeaki Okabe ,  Isao Yoshida ,  Mineo Katsueda ,  Hidefumi Ito ,  Masatomo Furumi ,  Shikayuki Ochi

IPC分类号： H03F1/52 ,  H01L27/02 ,  H01L27/06 ,  H01L29/78 ,  H03F1/42

CPC分类号： H01L27/0251

摘要： An insulated-gate semiconductor device wherein a first region is formed in the surface of a semiconductor substrate, the first region having a conductivity type opposite to that of the substrate, two insulated-gate FET's are formed within the first region, the drain of the first insulated-gate FET and that of the second insulated-gate FET are made common, the drains are electrically connected to the first region, and the gate of the first insulated-gate FET and the source of the second insulated-gate FET, and the gate of the second insulated-gate FET and the source of the first insulated-gate FET are respectively connected, thereby to prevent the occurrence of a negative resistance.

摘要翻译： 一种绝缘栅半导体器件，其中第一区域形成在半导体衬底的表面中，所述第一区域具有与衬底的导电类型相反的导电类型，在所述第一区域内形成有两个绝缘栅FET， 第一绝缘栅极FET和第二绝缘栅极FET的漏极共同，漏极电连接到第一区域，第一绝缘栅极FET的栅极和第二绝缘栅极FET的源极，以及 第二绝缘栅FET的栅极和第一绝缘栅FET的源极分别连接，从而防止产生负电阻。

公开(公告)号：US4599576A

公开(公告)日：1986-07-08

申请号：US882625

申请日：1978-03-01

申请人： Isao Yoshida ,  Takeaki Okabe ,  Shikayuki Ochi ,  Hidefumi Ito ,  Masatomo Furumi ,  Masaru Takeuchi ,  Minoru Nagata

发明人： Isao Yoshida ,  Takeaki Okabe ,  Shikayuki Ochi ,  Hidefumi Ito ,  Masatomo Furumi ,  Masaru Takeuchi ,  Minoru Nagata

IPC分类号： H01L21/8238 ,  H01L27/02 ,  H01L27/092 ,  H01L29/78 ,  H03F3/30 ,  H03F3/16 ,  H03F3/18

CPC分类号： H03F3/3001 ,  H01L27/0251 ,  H01L27/092 ,  H01L29/78 ,  H01L29/7835 ,  H01L2224/48472 ,  H01L2924/1305 ,  H01L2924/13091

摘要： An insulated gate type field effect transistor for high power which has a low conductivity region surrounding a drain region and an offset gate region having a further lower conductivity adjoined thereto, wherein the length and impurity concentration are designed according to the electric characteristics of the transistor. A combination of P channel and N channel type transistors having substantially the same electric characteristics and an audio amplifying circuit using the combination are also disclosed.

摘要翻译： 一种用于高功率的绝缘栅型场效应晶体管，其具有围绕漏极区域的低导电性区域和与其相邻的更低导电率的偏移栅极区域，其中根据晶体管的电特性设计长度和杂质浓度。 还公开了具有基本相同电特性的P沟道和N沟道型晶体管的组合以及使用该组合的音频放大电路。

公开(公告)号：US4492974A

公开(公告)日：1985-01-08

申请号：US350589

申请日：1982-02-22

申请人： Isao Yoshida ,  Takeaki Okabe ,  Mineo Katsueda ,  Minoru Nagata ,  Toshiaki Masuhara ,  Kazutoshi Ashikawa ,  Hideaki Kato ,  Mitsuo Ito ,  Shigeo Ohtaka ,  Osamu Minato ,  Yoshio Sakai

发明人： Isao Yoshida ,  Takeaki Okabe ,  Mineo Katsueda ,  Minoru Nagata ,  Toshiaki Masuhara ,  Kazutoshi Ashikawa ,  Hideaki Kato ,  Mitsuo Ito ,  Shigeo Ohtaka ,  Osamu Minato ,  Yoshio Sakai

IPC分类号： H01L27/02 ,  H01L27/04 ,  H01L27/06 ,  H01L29/78 ,  H01L29/861 ,  H01L29/90 ,  H02H3/20

CPC分类号： H01L29/7811 ,  H01L27/0255 ,  H01L27/0688 ,  H01L29/7808 ,  H01L29/861 ,  H01L2924/0002

摘要： A semiconductor integrated circuit device is provided to include a vertical type MOSFET and a gate protection element for the MOSFET. The vertical type MOSFET is made up of a silicon layer of n-type conductivity formed on an n.sup.+ -type silicon substrate, a base region of p-type conductivity formed in the surface of the silicon layer of n-type conductivity, an n.sup.+ -type source region provided in the base region, and a gate electrode formed on a portion of the base region through a gate insulating film. The silicon substrate serves as the drain. The gate protection element is formed of a polycrystalline silicon layer which is provided on the base region through an insulating film and includes at least one pn junction. By virtue of forming the gate protection element over the base region rather than directly over the substrate, a more stable operation is achieved.

摘要翻译： 提供半导体集成电路器件以包括用于MOSFET的垂直型MOSFET和栅极保护元件。 垂直型MOSFET由n +型硅衬底上形成的n型导电硅层，n型导电性硅层表面形成的p型导电基极区，n +型硅衬底， 设置在基极区域中的源极区，以及通过栅极绝缘膜形成在基极区域的一部分上的栅电极。 硅衬底用作漏极。 栅极保护元件由多晶硅层形成，该多晶硅层通过绝缘膜设置在基极区上并且包括至少一个pn结。 通过在基极区域而不是直接在衬底上形成栅极保护元件，实现更稳定的操作。

公开(公告)号：US4688323A

公开(公告)日：1987-08-25

申请号：US793243

申请日：1985-10-31

申请人： Isao Yoshida ,  Takeaki Okabe ,  Mitsuo Ito ,  Kazutoshi Ashikawa ,  Tetsuo Iijima

发明人： Isao Yoshida ,  Takeaki Okabe ,  Mitsuo Ito ,  Kazutoshi Ashikawa ,  Tetsuo Iijima

IPC分类号： H03F1/52 ,  H01L27/02 ,  H01L27/04 ,  H01L27/06 ,  H01L29/78 ,  H02H7/20 ,  H03F1/42 ,  H01L21/425 ,  H01L21/72

CPC分类号： H01L29/7808 ,  H01L27/0255 ,  H01L29/7811 ,  H01L29/0692 ,  H01L29/866 ,  H01L2924/0002

摘要： A method for fabrication a vertical MOSFET which contains a protective element for protecting the gate electrode of an insulated gate field effect transistor. The protective element is formed of the same semiconductor layer as that of the gate electrode of the insulated gate field effect transistor and is formed integrally with the gate electrode on an insulating film formed on the surface of a semiconductor substrate.

摘要翻译： 一种用于制造垂直MOSFET的方法，其包含用于保护绝缘栅场效应晶体管的栅电极的保护元件。 保护元件由与绝缘栅场效应晶体管的栅电极相同的半导体层形成，并与形成在半导体基板的表面上的绝缘膜上的栅电极一体形成。

公开(公告)号：US4172260A

公开(公告)日：1979-10-23

申请号：US853548

申请日：1977-11-21

申请人： Takeaki Okabe ,  Isao Yoshida ,  Shikayuki Ochi ,  Hidefumi Itoh ,  Masatomo Furumi ,  Toru Toyabe ,  Mineo Katsueda ,  Yukio Shirota

发明人： Takeaki Okabe ,  Isao Yoshida ,  Shikayuki Ochi ,  Hidefumi Itoh ,  Masatomo Furumi ,  Toru Toyabe ,  Mineo Katsueda ,  Yukio Shirota

IPC分类号： H01L21/331 ,  H01L29/06 ,  H01L29/40 ,  H01L29/41 ,  H01L29/73 ,  H01L29/78

CPC分类号： H01L29/404 ,  H01L29/7835

摘要： In an insulated gate field effect transistor having a source region and a drain region of the P-conductivity type which are disposed in surface portions of a semiconductor substrate of the N-conductivity type in a manner to be spaced apart from each other, a gate electrode being disposed through an insulating film on the substrate between the source region and the drain region, an insulated gate field effect transistor wherein said drain region is disposed apart from said gate electrode, two regions of an intermediate region and a high resistance region which are of the P-conductivity type and which successively extend from said drain region towards the side of said gate electrode are disposed in surface portions of the substrate situated between said drain region and said gate electrode, said intermediate region having an impurity concentration lower than that of said drain region, said high resistance region having an impurity concentration lower than that of said intermediate region, and a source electrode extends over and beyond said gate electrode and said high resistance region through said insulating film and terminates over said intermediate region.

摘要翻译： 在绝缘栅场效应晶体管中，具有P导电类型的源区和漏区，它们以相互间隔开的方式设置在N-导电类型的半导体衬底的表面部分中，栅极 电极通过源极区域和漏极区域之间的衬底上的绝缘膜设置，绝缘栅极场效应晶体管，其中所述漏极区域与所述栅电极隔开，中间区域和高电阻区域的两个区域是 的P导电类型并且从所述漏极区域朝向所述栅电极的侧面依次延伸设置在位于所述漏极区域和所述栅电极之间的衬底的表面部分中，所述中间区域的杂质浓度低于 所述漏极区，所述高电阻区的杂质浓度低于所述中间区的杂质浓度 并且源电极通过所述绝缘膜延伸超过所述栅电极和所述高电阻区域，并且终止于所述中间区域上。

公开(公告)号：US5299091A

公开(公告)日：1994-03-29

申请号：US854028

申请日：1992-03-19

申请人： Akio Hoshi ,  Yukihiro Sato ,  Toyomasa Koda ,  Isao Yoshida ,  Kouzou Sakamoto

发明人： Akio Hoshi ,  Yukihiro Sato ,  Toyomasa Koda ,  Isao Yoshida ,  Kouzou Sakamoto

IPC分类号： H01L23/34 ,  H01L23/36 ,  H01L23/433 ,  H01L23/495 ,  H05K1/02 ,  H05K1/11 ,  H05K3/34 ,  H05K7/20

CPC分类号： H01L23/36 ,  H01L23/4334 ,  H01L23/4951 ,  H01L23/49568 ,  H01L2224/16 ,  H01L2224/16245 ,  H01L2924/01014 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/3011 ,  H05K1/0201 ,  H05K1/111 ,  H05K3/3421 ,  Y10T29/49121

摘要： A packaged semiconductor device has, according to one embodiment of the present invention, a semiconductor pellet having an electronic circuit therein and electrode pads formed on a principal surface of the pellet, a plurality of electrical connection bumps provided on the electrode pads, a plurality of heat dissipation bumps provided at the principal surface of the pellet and electrically insulated from the electronic circuit and the electrode pads, electrical connection leads for the electronic circuit, heat dissipators for the electronic circuit and a packaging material for sealing pellet, the electrical connection bumps, the heat dissipation bumps and parts of the electrical connection leads and the heat dissipator. One or more of the heat dissipation bumps are arranged relatively nearer to the electronic circuit than the electrical connection bumps for thermal coupling to the electronic circuit. One or more of the electrical connection leads may be engaged with the electrical connection bumps and the heat dissipation bumps and/or one or more of the dissipators may be engaged with the heat dissipation bumps and the electrical connection bumps, thereby serving to effect electrical connection to and heat dissipation for the electronic circuit.

摘要翻译： 根据本发明的一个实施例，封装的半导体器件具有其中具有电子电路的半导体芯片和形成在芯片的主表面上的电极焊盘，设置在电极焊盘上的多个电连接凸块，多个 提供在颗粒主表面上的散热凸块与电子电路和电极焊盘电绝缘，用于电子电路的电气连接引线，用于电子电路的散热器和用于密封颗粒的包装材料，电连接凸块， 散热凸块和电气连接引线和散热器的部件。 一个或多个散热凸块被布置成比用于热耦合到电子电路的电连接凸块相对更靠近电子电路。 一个或多个电连接引线可以与电连接凸块接合，并且散热凸块和/或一个或多个散热器可以与散热凸块和电连接凸块接合，从而用于实现电连接 电子电路的散热和散热。

公开(公告)号：US06492872B1

公开(公告)日：2002-12-10

申请号：US09657237

申请日：2000-09-07

申请人： Toru Fujioka ,  Yoshikuni Matsunaga ,  Isao Yoshida ,  Masatoshi Morikawa ,  Masao Hotta ,  Tetsuaki Adachi

发明人： Toru Fujioka ,  Yoshikuni Matsunaga ,  Isao Yoshida ,  Masatoshi Morikawa ,  Masao Hotta ,  Tetsuaki Adachi

IPC分类号： H03G310

CPC分类号： H03F1/301 ,  H03G3/3042

摘要： A high frequency power amplifier module is provided for improving output controllability. A wireless communication apparatus incorporates a high frequency power amplifier module in a multi-stage configuration including a plurality of cascaded MOSFETS. The power amplifier module comprises a bias circuit for generating a gate voltage in response to a power control voltage (vapc) generated based on a power control signal of the wireless communication apparatus. The gate voltage has a bias pattern which presents smaller fluctuations in output power in response to a control voltage (Vapc) in a region near a threshold voltage (Vth) of the MOSFETs in respective amplification stages. In this way, the controllability for the output power is improved. More specifically, the power amplifier module has a gate bias circuit for generating the gate voltage (Vg) which follows a gate voltage pattern. The gate voltage (Vg) supplied to a control terminal in response to the control voltage (Vapc) largely changes in a region where the gate voltage (Vg) is lower than the threshold voltage (Vth) of the respective MOSFETs, and slightly changes near the threshold voltage (Vth). Also, the gate voltage (Vg) presents desired characteristics from the vicinity of the threshold voltage (Vth) to a high Vapc voltage region.

摘要翻译： 提供了一种用于提高输出可控性的高频功率放大器模块。 无线通信装置将包括多个级联MOSFET的多级配置的高频功率放大器模块结合在一起。 功率放大器模块包括用于响应于基于无线通信设备的功率控制信号产生的功率控制电压（vapc）产生栅极电压的偏置电路。 栅极电压具有偏置图案，其响应于在各个放大级中的MOSFET的阈值电压（Vth）附近的区域中的控制电压（Vapc），输出功率的波动较小。 以这种方式，提高了输出功率的可控性。 更具体地，功率放大器模块具有用于产生跟随栅极电压图案的栅极电压（Vg）的栅极偏置电路。 响应于控制电压（Vapc）而提供给控制端的栅极电压（Vg）在栅极电压（Vg）低于各个MOSFET的阈值电压（Vth）的区域内大大变化，并且稍微改变 阈值电压（Vth）。 此外，栅极电压（Vg）从阈值电压（Vth）附近到高Vapc电压区域呈现期望的特性。