公开(公告)号：US6100959A

公开(公告)日：2000-08-08

申请号：US50995

申请日：1998-03-31

申请人： Masayuki Kojima ,  Seiji Minamiyama

发明人： Masayuki Kojima ,  Seiji Minamiyama

IPC分类号： G03B27/46 ,  B65H29/02 ,  G03B27/32 ,  G03D13/00 ,  G03B27/00 ,  G03B27/52

CPC分类号： G03B27/32 ,  G03D13/003

摘要： A conveyor for a photo-processing apparatus having an exposing section and a developing section is disclosed. The conveyor conveys the photo-sensitive material from the exposing section to the developing section. A power source for conveying a photo-sensitive material in a vertical direction and a guide mechanism for guiding the photo-sensitive material in a lateral direction are installed in the conveyor. The lateral guidance of the photo-sensitive material by the guide mechanism is interlocked with the vertical conveyance by the power source to reduce the number of motors.

摘要翻译： 公开了一种用于具有曝光部分和显影部分的照相处理设备的输送机。 传送带将感光材料从曝光部分传送到显影部分。 用于沿垂直方向传送感光材料的电源和用于沿着横向引导感光材料的引导机构安装在输送机中。 通过引导机构的感光材料的横向引导与电源的垂直传送互锁，以减少电动机的数量。

公开(公告)号：US20100132392A1

公开(公告)日：2010-06-03

申请号：US12095107

申请日：2006-11-26

申请人： Masanao Yasutomi ,  Masayuki Kojima ,  Masuzou Takahashi ,  Toshihiro Wakamatsu

发明人： Masanao Yasutomi ,  Masayuki Kojima ,  Masuzou Takahashi ,  Toshihiro Wakamatsu

IPC分类号： F25D21/14 ,  F25D17/06

CPC分类号： F24F1/0007 ,  F24F1/0025 ,  F24F13/222

摘要： Grooves are formed on a back surface 22 of a tongue part 21 of a rear plate 3 which surface does not guide a flow of air.

摘要翻译： 凹槽形成在后板3的舌部21的后表面22上，该表面不引导空气流。

公开(公告)号：US07081649B2

公开(公告)日：2006-07-25

申请号：US10920389

申请日：2004-08-18

申请人： Kozo Watanabe ,  Atsushi Ogishima ,  Masahiro Moniwa ,  Syunichi Hashimoto ,  Masayuki Kojima ,  Kiyonori Ohyu ,  Kenichi Kuroda ,  Nozomu Matsuda

发明人： Kozo Watanabe ,  Atsushi Ogishima ,  Masahiro Moniwa ,  Syunichi Hashimoto ,  Masayuki Kojima ,  Kiyonori Ohyu ,  Kenichi Kuroda ,  Nozomu Matsuda

IPC分类号： H01L29/76

CPC分类号： H01L27/10852 ,  H01L27/105 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/10873 ,  H01L27/10888 ,  H01L27/10894 ,  Y10S257/90

摘要： A technology for a semiconductor integrated circuitry allows each of the DRAM memory cells to be divided finely so as to be more highly integrated and operate faster. In a method of manufacturing such a semiconductor integrated circuit, at first, gate electrodes 7 are formed via a gate insulating film 6 on the main surface of a semiconductor substrate 1, and on side surfaces of each of the gate electrodes there is formed a first side wall spacer 14 composed of silicon nitride and a second side wall spacer 15 composed of silicon oxide. Then, in the selecting MISFET Qs in the DRAM memory cell area there are opened connecting holes 19 and 21 in a self-matching manner with respect to the first side wall spacers 14 and connecting portion is formed connecting a conductor 20 to a bit line BL. In addition, in the N channel MISFETs Qn1 and Qn2, and in the P channel MISFET Qp1 in areas other than the DRAM memory cell area, high density N-type semiconductor areas 16 and 16b are formed, as well as a high density P-type semiconductor area 17 is formed in a self-matching manner with respect to the second side wall spacers 15.

摘要翻译： 用于半导体集成电路的技术允许每个DRAM存储单元被细分，以便更高度地集成并且操作更快。 在制造这样的半导体集成电路的方法中，首先，在半导体衬底1的主表面上经由栅极绝缘膜6形成栅电极7，并且在每个栅电极的侧表面上形成第一 由氮化硅构成的侧壁隔板14和由氧化硅构成的第二侧壁间隔物15。 然后，在DRAM存储单元区域中的选择MISFET Qs中，相对于第一侧壁间隔件14以自匹配的方式打开连接孔19和21，并且连接部分形成为将导体20连接到位线BL 。 此外，在N沟道MISFET Qn 1和Q n 2以及在DRAM存储单元区域以外的区域中的P沟道MISFET Qp 1中，形成高密度N型半导体区域16和16b，以及 高密度P型半导体区域17相对于第二侧壁间隔件15以自匹配的方式形成。

公开(公告)号：US06838388B2

公开(公告)日：2005-01-04

申请号：US09893577

申请日：2001-06-29

申请人： Masahiro Tadokoro ,  Masahiro Shioya ,  Masayuki Kojima ,  Takenobu Ikeda

发明人： Masahiro Tadokoro ,  Masahiro Shioya ,  Masayuki Kojima ,  Takenobu Ikeda

IPC分类号： H01L21/28 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/311 ,  H01L21/60 ,  H01L21/768 ,  H01L21/8242 ,  H01L27/108

CPC分类号： H01L21/76897 ,  H01L21/31116 ,  H01L21/31144 ,  H01L27/10855 ,  H01L27/10888

摘要： A fabrication method of a semiconductor integrated circuit device comprises, in an SAC process or HARC process, subjecting a semiconductor substrate to plasma etching to make contact holes in an oxide film made of a silicon oxide film formed on the semiconductor substrate. For improving the ease-in-etching property of the silicon oxide film and selectivity to a nitride film, a residence time of an etching gas within a chamber is so set as to be in a range where selectivity to an insulating film made of silicon nitride is improved by using etching conditions of a low pressure and a large flow rate of the etching gas of C5H8/O2/Ar.

公开(公告)号：US06743673B2

公开(公告)日：2004-06-01

申请号：US10145810

申请日：2002-05-16

申请人： Kozo Watanabe ,  Atsushi Ogishima ,  Masahiro Moniwa ,  Syunichi Hashimoto ,  Masayuki Kojima ,  Kiyonori Ohyu ,  Kenichi Kuroda ,  Nozomu Matsuda

发明人： Kozo Watanabe ,  Atsushi Ogishima ,  Masahiro Moniwa ,  Syunichi Hashimoto ,  Masayuki Kojima ,  Kiyonori Ohyu ,  Kenichi Kuroda ,  Nozomu Matsuda

IPC分类号： H01L218242

CPC分类号： H01L27/10852 ,  H01L27/105 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/10873 ,  H01L27/10888 ,  H01L27/10894 ,  Y10S257/90

摘要： A technology for a semiconductor integrated circuitry allows each of the DRAM memory cells to be divided finely so as to be more highly integrated and operate faster. In a method of manufacturing such a semiconductor integrated circuit, at first, gate electrodes 7 are formed via a gate insulating film 6 on the main surface of a semiconductor substrate 1, and on side surfaces of each of the gate electrodes there is formed a first side wall spacer 14 composed of silicon nitride and a second side wall spacer 15 composed of silicon oxide. Then, in the selecting MISFET Qs in the DRAM memory cell area there are opened connecting holes 19 and 21 in a self-matching manner with respect to the first side wall spacers 14 and connecting portion is formed connecting a conductor 20 to a bit line BL. In addition, in the N channel MISFETs Qn1 and Qn2, and in the P channel MISFET Qp1 in areas other than the DRAM memory cell area, high density N-type semiconductor areas 16 and 16b are formed, as well as a high density P-type semiconductor area 17 is formed in a self-matching manner with respect to the second side wall spacers 15.

摘要翻译： 用于半导体集成电路的技术允许每个DRAM存储单元被细分，以便更高度地集成并且操作更快。 在制造这样的半导体集成电路的方法中，首先，在半导体衬底1的主表面上经由栅极绝缘膜6形成栅电极7，并且在每个栅电极的侧表面上形成第一 由氮化硅构成的侧壁隔板14和由氧化硅构成的第二侧壁间隔物15。 然后，在DRAM存储单元区域中的选择MISFET Qs中，相对于第一侧壁间隔件14以自匹配的方式打开连接孔19和21，并且连接部分形成为将导体20连接到位线BL 。 此外，在N沟道MISFET Qn1和Qn2以及在DRAM存储单元区域以外的区域中的P沟道MISFET Qp1中，形成高密度N型半导体区域16和16b以及高密度P- 型半导体区域17相对于第二侧壁间隔件15以自匹配的方式形成。

公开(公告)号：US06537415B2

公开(公告)日：2003-03-25

申请号：US09942707

申请日：2001-08-31

申请人： Masayuki Kojima ,  Yoshimi Torii ,  Michimasa Hunabashi ,  Kazuyuki Suko ,  Takashi Yamada ,  Keizo Kuroiwa ,  Kazuo Nojiri ,  Yoshinao Kawasaki ,  Yoshiaki Sato ,  Ryooji Fukuyama ,  Hironobu Kawahara

发明人： Masayuki Kojima ,  Yoshimi Torii ,  Michimasa Hunabashi ,  Kazuyuki Suko ,  Takashi Yamada ,  Keizo Kuroiwa ,  Kazuo Nojiri ,  Yoshinao Kawasaki ,  Yoshiaki Sato ,  Ryooji Fukuyama ,  Hironobu Kawahara

IPC分类号： H01L213065

CPC分类号： H01L21/32136 ,  C23F4/00 ,  H01J37/185 ,  H01L21/67017 ,  H01L21/67028 ,  H01L21/67069 ,  H01L21/67161 ,  H01L21/67207 ,  H01L21/67745 ,  H01L21/67751

摘要： Disclosed is apparatus for treating samples, and a method of using the apparatus. The apparatus includes processing apparatus (a) for treating the samples (e.g., plasma etching apparatus), (b) for removing residual corrosive compounds formed by the sample treatment, (c) for wet-processing of the samples and (d) for dry-processing the samples. A plurality of wet-processing treatments of a sample can be performed. The wet-processing apparatus can include a plurality of wet-processing stations. The samples can either be passed in series through the plurality of wet-processing stations, or can be passed in parallel through the wet-processing stations.

公开(公告)号：US06254721B1

公开(公告)日：2001-07-03

申请号：US09504083

申请日：2000-02-15

申请人： Masayuki Kojima ,  Yoshimi Torii ,  Michimasa Hunabashi ,  Kazuyuki Suko ,  Takashi Yamada ,  Keizo Kuroiwa ,  Kazuo Nojiri ,  Yoshinao Kawasaki ,  Yoshiaki Sato ,  Ryooji Fukuyama ,  Hironobu Kawahara

发明人： Masayuki Kojima ,  Yoshimi Torii ,  Michimasa Hunabashi ,  Kazuyuki Suko ,  Takashi Yamada ,  Keizo Kuroiwa ,  Kazuo Nojiri ,  Yoshinao Kawasaki ,  Yoshiaki Sato ,  Ryooji Fukuyama ,  Hironobu Kawahara

IPC分类号： H01L21306

CPC分类号： H01L21/32136 ,  C23F4/00 ,  H01J37/185 ,  H01L21/67017 ,  H01L21/67028 ,  H01L21/67069 ,  H01L21/67161 ,  H01L21/67207 ,  H01L21/67745 ,  H01L21/67751

摘要： Disclosed is apparatus for treating samples, and a method of using the apparatus. The apparatus includes processing apparatus (a) for treating the samples (e.g., plasma etching apparatus), (b) for removing residual corrosive compounds formed by the sample treatment, (c) for wet-processing of the samples and (d) for dry-processing the samples. A plurality of wet-processing treatments of a sample can be performed. The wet-processing apparatus can include a plurality of wet-processing stations. The samples can either be passed in series through the plurality of wet-processing stations, or can be passed in parallel through the wet-processing stations.

摘要翻译： 公开了用于处理样品的装置以及使用该装置的方法。 该设备包括用于处理样品（例如，等离子体蚀刻设备）的处理设备（a），（b）用于除去由样品处理形成的残余腐蚀性化合物，（c）用于湿法处理样品和（d）干燥 处理样品。 可以进行多个样品的湿法处理。 湿式处理装置可以包括多个湿加工站。 样品可以通过多个湿处理站串联通过，或者可以通过湿处理站并行通过。

公开(公告)号：US06191045B1

公开(公告)日：2001-02-20

申请号：US09302438

申请日：1999-04-30

申请人： Motohiko Yoshigai ,  Hiroshi Hasegawa ,  Hiroshi Akiyama ,  Takafumi Tokunaga ,  Tadashi Umezawa ,  Masayuki Kojima ,  Kazuo Nojiri ,  Hiroshi Kawakami ,  Kunihiko Katou

发明人： Motohiko Yoshigai ,  Hiroshi Hasegawa ,  Hiroshi Akiyama ,  Takafumi Tokunaga ,  Tadashi Umezawa ,  Masayuki Kojima ,  Kazuo Nojiri ,  Hiroshi Kawakami ,  Kunihiko Katou

IPC分类号： H01L2100

CPC分类号： H01L21/67069 ,  H01L21/32136 ,  H01L21/32137

摘要： In order to provide a method of treating a multilayer including metal and polysilicon for use in a conductor or a gate electrode of a semiconductor device with high accuracy at a high selectivity, the temperature of a sample is maintained at 100° C. or higher at the time of etching a metal film to increase the etch rate of the metal film. In order to suppress the etch rate of a polysilicon film and prevent side etching, an oxygen gas is added to a gas containing a halogen element. In order to suppress the etch rate of a silicon oxide film at the time of etching the polysilicon film, the etching is performed with etch parameters which are divided into those for the metal film and those for the polysilicon film. In the etching performed to the multilayer containing metal and polysilicon, by etching the metal film at a high temperature of 100° C. or higher, the etch rate of the metal film becomes high. Consequently, there is no partial etch residue of the metal film and a barrier film. By switching the parameters to those with which the polysilicon film can be etched at a high selectivity with respect to an oxide film at the time point of completion of etching to the barrier film, very accurate treatment can be realized.

摘要翻译： 为了提供以高选择性以高精度处理用于半导体器件的导体或栅电极的金属和多晶硅的多层的方法，将样品的温度保持在100℃以上 蚀刻金属膜以增加金属膜的蚀刻速率的时间。 为了抑制多晶硅膜的蚀刻速度并防止侧面蚀刻，将氧气添加到含有卤素元素的气体中。 为了抑制蚀刻多晶硅膜时的氧化硅膜的蚀刻速率，用蚀刻参数进行蚀刻，蚀刻参数分为金属膜和多晶硅膜蚀刻参数。 在对多层容纳金属和多晶硅进行的蚀刻中，通过在100℃以上的高温下蚀刻金属膜，金属膜的蚀刻速度变高。 因此，不存在金属膜和阻挡膜的部分蚀刻残留。 通过在对阻挡膜的蚀刻完成时刻将参数切换为能够以相对于氧化膜的高选择性蚀刻多晶硅膜的参数，可以实现非常精确的处理。

公开(公告)号：US5754915A

公开(公告)日：1998-05-19

申请号：US750676

申请日：1996-12-13

申请人： Shigeru Masuda ,  Tsukasa Nakano ,  Masayuki Kojima ,  Masayuki Nakanishi ,  Toshihiko Nakano ,  Haruo Hakamada ,  Hideo Ishii

发明人： Shigeru Masuda ,  Tsukasa Nakano ,  Masayuki Kojima ,  Masayuki Nakanishi ,  Toshihiko Nakano ,  Haruo Hakamada ,  Hideo Ishii

IPC分类号： G03D3/06

CPC分类号： G03D3/065

摘要： An automatic photosensitive material developing machine supplies a solid processing solution to be dissolved according to consumption of processing solution for a silver halide photosensitive material to be treated. The developing machine includes a solid processing solution supplying section for supplying the solid processing solution from a solid processing solution cartridge containing the solid processing solution, and a solid processing solution transferring section for receiving the solid processing solution supplied by the solid processing solution supplying section in a bucket, and for transferring the bucket upward.

摘要翻译： PCT No.PCT / JP95 / 01188 Sec。 371日期1996年12月13日第 102（e）日期1996年12月13日PCT提交1995年6月12日PCT公布。 WO95 / 34844 PCT出版物 日期1995年12月21日自动感光材料显影机根据消费用于待处理的卤化银感光材料的处理溶液提供待溶解的固体处理溶液。 显影机包括：固体处理剂供给部，用于从固体处理溶液的固体处理液筒供给固体处理液;固体处理液转移部，其用于接收由固体处理剂供给部供给的固体处理液 一个铲斗，并将铲斗向上传送。

公开(公告)号：US5475463A

公开(公告)日：1995-12-12

申请号：US219935

申请日：1994-03-30

申请人： Takuji Yamaguchi ,  Tohgo Kinoshita ,  Yasunobu Shimamura ,  Yuji Yamazoe ,  Shinji Fukushima ,  Masayuki Kojima

发明人： Takuji Yamaguchi ,  Tohgo Kinoshita ,  Yasunobu Shimamura ,  Yuji Yamazoe ,  Shinji Fukushima ,  Masayuki Kojima

IPC分类号： G03D3/13 ,  G03D13/00 ,  G03D3/08

CPC分类号： G03D13/003 ,  G03D3/135

摘要： Various arrangements are proposed for coupling films to a leader. A hole is formed in one of the films and the leader to receive a tab which is formed on the other. These arrangements allow stable coupling of the films to the leader and easy uncoupling. They eliminate the use of splice tape.

摘要翻译： 提出了将膜耦合到引导件的各种布置。 在一个膜和引导件中形成孔，以接收在另一个上形成的突片。 这些布置允许膜稳定地连接到引导件并且易于解耦。 它们消除了使用拼接胶带。