公开(公告)号：US11127899B2

公开(公告)日：2021-09-21

申请号：US16382026

申请日：2019-04-11

Applicant: Micron Technology, inc.

Inventor： Jordan D. Greenlee ,  Tao D. Nguyen ,  John Mark Meldrim ,  Aaron K. Belsher

IPC: G11C5/06 ,  H01L45/00 ,  H01L27/24 ,  G11C13/00

Abstract: Some embodiments include an integrated assembly having an insulative mass over a conductive base structure. A conductive interconnect extends through the insulative mass to an upper surface of the conductive base structure. The conductive interconnect includes a conductive liner extending around an outer lateral periphery of the interconnect. The conductive liner includes nitrogen in combination with a first metal. A container-shaped conductive structure is laterally surrounded by the conductive liner. The container-shaped conductive structure includes a second metal. A conductive plug is within the container-shaped conductive structure. Some embodiments include methods of forming conductive interconnects within integrated assemblies.

公开(公告)号：US11031417B2

公开(公告)日：2021-06-08

申请号：US16903201

申请日：2020-06-16

Applicant: Micron Technology, Inc.

Inventor： Jordan D. Greenlee ,  John Mark Meldrim ,  E. Allen McTeer

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/11565

Abstract: A method used in forming an array of elevationally-extending transistors comprises forming vertically-alternating tiers of insulating material and void space. Such method includes forming (a) individual longitudinally-aligned channel openings extending elevationally through the insulating-material tiers, and (b) horizontally-elongated trenches extending elevationally through the insulating-material tiers. The void-space tiers are filled with conductive material by flowing the conductive material or one or more precursors thereof through at least one of (a) and (b) to into the void-space tiers. After the filling, transistor channel material is formed in the individual channel openings along the insulating-material tiers and along the conductive material in the filled void-space tiers.

公开(公告)号：US20210091009A1

公开(公告)日：2021-03-25

申请号：US16579577

申请日：2019-09-23

Applicant: Micron Technology, Inc.

Inventor： Devesh Kumar Datta ,  David Daycock ,  Keen Wah Chow ,  Tom George ,  Justin B. Dorhout ,  Bingli Ma ,  Rita J. Klein ,  John Mark Meldrim

IPC: H01L23/532 ,  H01L23/522 ,  H01L23/528 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11565 ,  H01L27/1157

Abstract: Some embodiments include a memory device having a conductive structure which includes silicon-containing material. A stack is over the conductive structure and includes alternating insulative levels and conductive levels. Channel material pillars extend through the stack and are electrically coupled with the conductive structure. Memory cells are along the channel material pillars. A conductive barrier material is under the silicon-containing material. The conductive barrier material includes one or more metals in combination with one or more nonmetals. An electrical contact is under the conductive barrier material. The electrical contact includes a region reactive with silicon. Silicon is precluded from reaching said region at least in part due to the conductive barrier material. Control circuitry is under the electrical contact and is electrically coupled with the conductive structure through at least the electrical contact and the conductive barrier material.

公开(公告)号：US20200152651A1

公开(公告)日：2020-05-14

申请号：US16736089

申请日：2020-01-07

Applicant: Micron Technology, Inc.

Inventor： Jordan D. Greenlee ,  John Mark Meldrim ,  Everett A. McTeer

IPC: H01L27/11556 ,  H01L27/11565 ,  H01L21/285 ,  H01L27/11582

Abstract: Some embodiments include a method in which an assembly is formed to have voids within a stack, and to have slits adjacent the voids. Peripheral boundaries of the voids have proximal regions near the slits and distal regions adjacent the proximal regions. A material is deposited within the voids under conditions which cause the material to form to a greater thickness along the distal regions than along the proximal regions. Some embodiments include an assembly having a stack of alternating first and second levels. The second levels include conductive material. Panel structures extend through the stack. The conductive material within the second levels has outer edges with proximal regions near the panel structures and distal regions adjacent the proximal regions. Interface material is along the outer edges of the conductive material and has a different composition along the proximal regions than along the distal regions.

公开(公告)号：US20190221580A1

公开(公告)日：2019-07-18

申请号：US16363296

申请日：2019-03-25

Applicant: Micron Technology, Inc.

Inventor： Jordan D. Greenlee ,  Chet E. Carter ,  Collin Howder ,  John Mark Meldrim ,  Everett A. McTeer

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L21/28 ,  H01L21/3213 ,  H01L29/10 ,  H01L21/768 ,  H01L23/528 ,  H01L21/285 ,  H01L23/532

CPC classification number: H01L27/11582 ,  H01L21/28568 ,  H01L21/32134 ,  H01L21/76843 ,  H01L21/76877 ,  H01L23/5283 ,  H01L23/53266 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565 ,  H01L29/1037 ,  H01L29/40114 ,  H01L29/40117 ,  H01L29/4966 ,  H01L29/4975

Abstract: Some embodiments include a method of forming an integrated structure. An assembly is formed to include a stack of alternating first and second levels. The first levels have insulative material, and the second levels have voids which extend horizontally. The assembly includes channel material structures extending through the stack. A first metal-containing material is deposited within the voids to partially fill the voids. The deposited first metal-containing material is etched to remove some of the first metal-containing material from within the partially-filled voids. Second metal-containing material is then deposited to fill the voids.

公开(公告)号：US10354989B1

公开(公告)日：2019-07-16

申请号：US15980908

申请日：2018-05-16

Applicant: Micron Technology, Inc.

Inventor： Daniel Billingsley ,  Everett A. McTeer ,  Christopher W. Petz ,  Haoyu Li ,  John Mark Meldrim ,  Yongjun Jeff Hu

IPC: G11C11/34 ,  H01L27/02 ,  H01L23/532 ,  G11C5/06 ,  H01L27/12 ,  H01L21/82

Abstract: An integrated assembly having an insulative mass with a first region adjacent to a second region. The first region has a greater amount of one or more inert interstitial elements incorporated therein than does the second region. Also, an integrated assembly which has vertically-extending channel material pillars, and which has memory cells along the channel material pillars. A conductive structure is under the channel material pillars. The conductive structure includes doped semiconductor material in direct contact with bottom regions of the channel material pillars. An insulative mass is along the bottom regions of the channel material pillars. The insulative mass has an upper region over a lower region. The lower region has a greater amount of one or more inert interstitial elements incorporated therein than does the upper region. Also, methods of forming integrated assemblies.

公开(公告)号：US09608185B2

公开(公告)日：2017-03-28

申请号：US14261901

申请日：2014-04-25

Applicant: Micron Technology, Inc.

Inventor： Yongjun Jeff Hu ,  John Mark Meldrim ,  Shanming Mou ,  Everett Allen McTeer

IPC: H01L33/62 ,  H01L33/40 ,  H01L33/32 ,  H01L33/46

CPC classification number: H01L33/62 ,  H01L33/0066 ,  H01L33/0075 ,  H01L33/32 ,  H01L33/40 ,  H01L33/46 ,  H01L2924/0002 ,  H01L2933/0016 ,  H01L2933/0066 ,  H01L2924/00

Abstract: A composition and method for formation of ohmic contacts on a semiconductor structure are provided. The composition includes a TiAlxNy material at least partially contiguous with the semiconductor structure. The TiAlxNy material can be TiAl3. The composition can include an aluminum material, the aluminum material being contiguous to at least part of the TiAlxNy material, such that the TiAlxNy material is between the aluminum material and the semiconductor structure. The method includes annealing the composition to form an ohmic contact on the semiconductor structure.

公开(公告)号：US20140234996A1

公开(公告)日：2014-08-21

申请号：US14261901

申请日：2014-04-25

Applicant: Micron Technology, Inc.

Inventor： Yongjun Jeff Hu ,  John Mark Meldrim ,  Shanming Mou ,  Everett Allen McTeer

IPC: H01L33/62

CPC classification number: H01L33/62 ,  H01L33/0066 ,  H01L33/0075 ,  H01L33/32 ,  H01L33/40 ,  H01L33/46 ,  H01L2924/0002 ,  H01L2933/0016 ,  H01L2933/0066 ,  H01L2924/00

Abstract: A composition and method for formation of ohmic contacts on a semiconductor structure are provided. The composition includes a TiAlxNy material at least partially contiguous with the semiconductor structure. The TiAlxNy material can be TiAl3. The composition can include an aluminum material, the aluminum material being contiguous to at least part of the TiAlxNy material, such that the TiAlxNy material is between the aluminum material and the semiconductor structure. The method includes annealing the composition to form an ohmic contact on the semiconductor structure.

Abstract translation: 提供了一种在半导体结构上形成欧姆接触的组合物和方法。 该组合物包括与半导体结构至少部分邻接的TiAl x N y材料。 TiAlxNy材料可以是TiAl3。 组合物可以包括铝材料，铝材料与TiAl x N y材料的至少一部分相邻，使得TiAl x N y材料在铝材料和半导体结构之间。 该方法包括退火组合物以在半导体结构上形成欧姆接触。

公开(公告)号：US12295140B2

公开(公告)日：2025-05-06

申请号：US17533580

申请日：2021-11-23

Applicant: Micron Technology, Inc.

Inventor： Jordan D. Greenlee ,  Allen McTeer ,  Rita J. Klein ,  John D. Hopkins ,  Nancy M. Lomeli ,  Xiao Li ,  Alyssa N. Scarbrough ,  Jiewei Chen ,  Naiming Liu ,  Shuangqiang Luo ,  Silvia Borsari ,  John Mark Meldrim ,  Shen Hu

IPC: H10B41/27 ,  H10B41/35 ,  H10B43/27 ,  H10B43/35

Abstract: A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Strings of memory cells comprise channel-material strings that extend through the insulative tiers and the conductive tiers in the memory blocks. A through-array-via (TAV) region comprises TAV constructions that extend through the insulative tiers and the conductive tiers. The TAV constructions individually comprise a radially-outer insulative lining and a conductive core radially-inward of the insulative lining. The insulative lining comprises a radially-inner insulative material and a radially-outer insulative material that are of different compositions relative one another. The radially-outer insulative material is in radially-outer recesses that are in the first tiers as compared to the second tiers. The radially-inner insulative material extends elevationally along the insulative tiers and the conductive tiers. Other embodiments, including method, are disclosed.

公开(公告)号：US12114492B2

公开(公告)日：2024-10-08

申请号：US17071980

申请日：2020-10-15

Applicant: Micron Technology, Inc.

Inventor： Jordan D. Greenlee ,  John Mark Meldrim ,  Everett A. McTeer

IPC: H10B43/27 ,  H01L21/285 ,  H10B41/27 ,  H10B43/10 ,  H10B41/10

CPC classification number: H10B41/27 ,  H01L21/28562 ,  H10B43/10 ,  H10B43/27 ,  H01L21/28518 ,  H01L21/28568 ,  H10B41/10

Abstract: Some embodiments include a method in which an assembly is formed to have voids within a stack, and to have slits adjacent the voids. Peripheral boundaries of the voids have proximal regions near the slits and distal regions adjacent the proximal regions. A material is deposited within the voids under conditions which cause the material to form to a greater thickness along the distal regions than along the proximal regions. Some embodiments include an assembly having a stack of alternating first and second levels. The second levels include conductive material. Panel structures extend through the stack. The conductive material within the second levels has outer edges with proximal regions near the panel structures and distal regions adjacent the proximal regions. Interface material is along the outer edges of the conductive material and has a different composition along the proximal regions than along the distal regions.