公开(公告)号：US10978427B2

公开(公告)日：2021-04-13

申请号：US16592420

申请日：2019-10-03

Applicant: Micron Technology, Inc.

Inventor： Jian Li ,  Steven K. Groothuis

IPC: H01L25/065 ,  H01L25/00 ,  H01L25/18 ,  G11C7/04 ,  H01L23/498 ,  H01L23/367 ,  H01L23/00

Abstract: Stacked semiconductor die assemblies having memory dies stacked between partitioned logic dies and associated systems and methods are disclosed herein. In one embodiment, a semiconductor die assembly can include a first logic die, a second logic die, and a thermally conductive casing defining an enclosure. The stack of memory dies can be disposed within the enclosure and between the first and second logic dies.

公开(公告)号：US20200141658A1

公开(公告)日：2020-05-07

申请号：US16726735

申请日：2019-12-24

Applicant: Micron Technology, Inc.

Inventor： Steven K. Groothuis ,  Jian Li

IPC: F28D15/04 ,  F28D15/02 ,  H01L23/427 ,  H01L23/367

Abstract: Semiconductor device assemblies having stacked semiconductor dies and thermal transfer devices that include vapor chambers are disclosed herein. In one embodiment, a semiconductor device assembly includes a first semiconductor die, a second semiconductor die on a base region of the first die, and a thermal transfer device attached to a peripheral region of the first die and extending over the second die. The thermal transfer device includes a conductive structure having an internal cavity and a working fluid at least partially filling the cavity. The conductive structure further includes first and second fluid conversion regions adjacent the cavity. The first fluid conversion region transfers heat from at least the peripheral region of the first die to a volume of the working fluid to vaporize the volume in the cavity, and the second fluid conversion region condenses the volume of the working fluid in the cavity after it has been vaporized.

公开(公告)号：US20160013173A1

公开(公告)日：2016-01-14

申请号：US14330805

申请日：2014-07-14

Applicant: Micron Technology, Inc.

Inventor： Sameer S. Vadhavkar ,  Xiao Li ,  Steven K. Groothuis ,  Jian Li ,  Jaspreet S. Gandhi ,  James M. Derderian ,  David R. Hembree

IPC: H01L25/00 ,  H01L23/00 ,  H01L21/56

CPC classification number: H01L25/50 ,  H01L21/50 ,  H01L21/563 ,  H01L23/04 ,  H01L23/3675 ,  H01L23/44 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/83 ,  H01L24/92 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/1134 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/1329 ,  H01L2224/133 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/1703 ,  H01L2224/17181 ,  H01L2224/17519 ,  H01L2224/2919 ,  H01L2224/29191 ,  H01L2224/2929 ,  H01L2224/2939 ,  H01L2224/29393 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/83101 ,  H01L2224/83102 ,  H01L2224/83104 ,  H01L2224/83424 ,  H01L2224/83447 ,  H01L2224/8388 ,  H01L2224/92125 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/156 ,  H01L2924/16235 ,  H01L2924/16251 ,  H01L2924/1815 ,  H01L2924/0715 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/014 ,  H01L2924/01047 ,  H01L2924/00012 ,  H01L2924/0665 ,  H01L2924/00

Abstract: Method for packaging a semiconductor die assemblies. In one embodiment, a method is directed to packaging a semiconductor die assembly having a first die and a plurality of second dies arranged in a stack over the first die, wherein the first die has a peripheral region extending laterally outward from the stack of second dies. The method can comprise coupling a thermal transfer structure to the peripheral region of the first die and flowing an underfill material between the second dies. The underfill material is flowed after coupling the thermal transfer structure to the peripheral region of the first die such that the thermal transfer structure limits lateral flow of the underfill material.

Abstract translation: 封装半导体管芯组件的方法。 在一个实施例中，一种方法涉及将具有第一管芯和多个第二管芯的半导体管芯组件封装在第一管芯上，其中第一管芯具有从第二管芯的堆叠体横向向外延伸的周边区域 。 该方法可以包括将热传递结构耦合到第一模具的周边区域并且在第二模具之间流动底部填充材料。 在将热传递结构连接到第一模具的周边区域之后，底部填充材料流动，使得热转印结构限制底部填充材料的横向流动。

公开(公告)号：US20230395463A1

公开(公告)日：2023-12-07

申请号：US18454703

申请日：2023-08-23

Applicant: Micron Technology, Inc.

Inventor： Sameer S. Vadhavkar ,  Xiao Li ,  Steven K. Groothuis ,  Jian Li ,  Jaspreet S. Gandhi ,  James M. Derderian ,  David R. Hembree

IPC: H01L23/44 ,  H01L25/00 ,  H01L21/56 ,  H01L23/00 ,  H01L23/367 ,  H01L25/18 ,  H01L23/04 ,  H01L21/50 ,  H01L25/065 ,  H01L23/373 ,  H01L21/52 ,  H01L21/54 ,  H01L23/053 ,  H01L23/31

CPC classification number: H01L23/44 ,  H01L25/50 ,  H01L21/563 ,  H01L24/83 ,  H01L23/3675 ,  H01L25/18 ,  H01L23/04 ,  H01L21/50 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/92 ,  H01L25/0657 ,  H01L23/3736 ,  H01L24/73 ,  H01L21/52 ,  H01L21/54 ,  H01L23/053 ,  H01L23/3128 ,  H01L2924/156 ,  H01L2924/1815 ,  H01L2224/1703 ,  H01L2224/32145 ,  H01L2224/73203 ,  H01L2224/73253 ,  H01L2225/06517 ,  H01L2225/06589 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/16235 ,  H01L2924/16251 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2224/17519 ,  H01L2224/2939 ,  H01L24/29 ,  H01L24/33 ,  H01L2224/1134 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/133 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/2919 ,  H01L2224/29191 ,  H01L2224/2929 ,  H01L2224/29393 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/83101 ,  H01L2224/83102 ,  H01L2224/83424 ,  H01L2224/83447 ,  H01L2224/8388 ,  H01L2224/92125 ,  H01L2924/15311 ,  H01L2224/83104 ,  H01L2224/1329

Abstract: Method for packaging a semiconductor die assemblies. In one embodiment, a method is directed to packaging a semiconductor die assembly having a first die and a plurality of second dies arranged in a stack over the first die, wherein the first die has a peripheral region extending laterally outward from the stack of second dies. The method can comprise coupling a thermal transfer structure to the peripheral region of the first die and flowing an underfill material between the second dies. The underfill material is flowed after coupling the thermal transfer structure to the peripheral region of the first die such that the thermal transfer structure limits lateral flow of the underfill material.

公开(公告)号：US11594462B2

公开(公告)日：2023-02-28

申请号：US16936639

申请日：2020-07-23

Applicant: Micron Technology, Inc.

Inventor： Steven K. Groothuis ,  Jian Li ,  Haojun Zhang ,  Paul A. Silvestri ,  Xiao Li ,  Shijian Luo ,  Luke G. England ,  Brent Keeth ,  Jaspreet S. Gandhi

IPC: H01L23/36 ,  H01L23/367 ,  H01L23/373 ,  H01L23/42 ,  H01L25/065 ,  H01L25/18 ,  H01L25/00

Abstract: Stacked semiconductor die assemblies with multiple thermal paths and associated systems and methods are disclosed herein. In one embodiment, a semiconductor die assembly can include a plurality of first semiconductor dies arranged in a stack and a second semiconductor die carrying the first semiconductor dies. The second semiconductor die can include a peripheral portion that extends laterally outward beyond at least one side of the first semiconductor dies. The semiconductor die assembly can further include a thermal transfer feature at the peripheral portion of the second semiconductor die. The first semiconductor dies can define a first thermal path, and the thermal transfer feature can define a second thermal path separate from the first semiconductor dies.

公开(公告)号：US10741468B2

公开(公告)日：2020-08-11

申请号：US16229257

申请日：2018-12-21

Applicant: Micron Technology, Inc.

Inventor： Steven K. Groothuis ,  Jian Li ,  Haojun Zhang ,  Paul A. Silvestri ,  Xiao Li ,  Shijian Luo ,  Luke G. England ,  Brent Keeth ,  Jaspreet S. Gandhi

IPC: H01L23/36 ,  H01L23/367 ,  H01L23/42 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18 ,  H01L23/373

Abstract: Stacked semiconductor die assemblies with multiple thermal paths and associated systems and methods are disclosed herein. In one embodiment, a semiconductor die assembly can include a plurality of first semiconductor dies arranged in a stack and a second semiconductor die carrying the first semiconductor dies. The second semiconductor die can include a peripheral portion that extends laterally outward beyond at least one side of the first semiconductor dies. The semiconductor die assembly can further include a thermal transfer feature at the peripheral portion of the second semiconductor die. The first semiconductor dies can define a first thermal path, and the thermal transfer feature can define a second thermal path separate from the first semiconductor dies.

公开(公告)号：US20190145713A1

公开(公告)日：2019-05-16

申请号：US16247352

申请日：2019-01-14

Applicant: Micron Technology, Inc.

Inventor： Steven K. Groothuis ,  Jian Li

IPC: F28D15/04 ,  H01L23/427 ,  H01L23/367 ,  F28D15/02

CPC classification number: F28D15/043 ,  F28D15/0233 ,  F28D15/0266 ,  F28D15/046 ,  H01L23/3675 ,  H01L23/427 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1438 ,  H01L2924/16235 ,  H01L2924/16251 ,  H01L2924/1632 ,  H01L2924/014 ,  H01L2924/00014

Abstract: Semiconductor device assemblies having stacked semiconductor dies and thermal transfer devices that include vapor chambers are disclosed herein. In one embodiment, a semiconductor device assembly includes a first semiconductor die, a second semiconductor die on a base region of the first die, and a thermal transfer device attached to a peripheral region of the first die and extending over the second die. The thermal transfer device includes a conductive structure having an internal cavity and a working fluid at least partially filling the cavity. The conductive structure further includes first and second fluid conversion regions adjacent the cavity. The first fluid conversion region transfers heat from at least the peripheral region of the first die to a volume of the working fluid to vaporize the volume in the cavity, and the second fluid conversion region condenses the volume of the working fluid in the cavity after it has been vaporized.

公开(公告)号：US09837396B2

公开(公告)日：2017-12-05

申请号：US15254586

申请日：2016-09-01

Applicant: Micron Technology, Inc.

Inventor： Sameer S. Vadhavkar ,  Xiao Li ,  Steven K. Groothuis ,  Jian Li ,  Jaspreet S. Gandhi ,  James M. Derderian ,  David R. Hembree

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L25/00 ,  H01L25/065 ,  H01L25/16 ,  H01L21/56 ,  H01L23/04 ,  H01L21/50 ,  H01L23/36 ,  H01L23/367 ,  H01L21/48

CPC classification number: H01L25/50 ,  H01L21/4882 ,  H01L21/50 ,  H01L21/563 ,  H01L23/04 ,  H01L23/36 ,  H01L23/3675 ,  H01L25/0657 ,  H01L25/16 ,  H01L25/167 ,  H01L2224/16145 ,  H01L2225/06568 ,  H01L2225/06589

Abstract: A semiconductor die assembly having high efficiency thermal paths. In one embodiment, the semiconductor die assembly comprises a package support substrate, a first semiconductor die having a peripheral region and a stacking region, and a second semiconductor die attached to the stacking region of the first die such that the peripheral region is lateral of the second die. The assembly further includes a thermal transfer unit having a base attached to the peripheral region of the first die, a cover attached to the base by an adhesive, and a cavity defined by at least cover, wherein the second die is within the cavity. The assembly also includes an underfill in the cavity, wherein a fillet portion of the underfill extends a distance up along a portion of the footing and upward along at least a portion of the base.

公开(公告)号：US09780079B2

公开(公告)日：2017-10-03

申请号：US14700222

申请日：2015-04-30

Applicant: Micron Technology, Inc.

Inventor： Jian Li ,  Steven K. Groothuis

IPC: H01L23/34 ,  H01L25/18 ,  H01L25/065 ,  H01L23/367 ,  H01L25/00 ,  H01L23/055 ,  H01L23/13 ,  H01L23/00 ,  H01L21/683

CPC classification number: H01L25/18 ,  H01L21/6835 ,  H01L23/055 ,  H01L23/13 ,  H01L23/3675 ,  H01L23/3677 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/33 ,  H01L24/73 ,  H01L24/83 ,  H01L24/92 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68331 ,  H01L2224/0401 ,  H01L2224/05082 ,  H01L2224/05147 ,  H01L2224/05171 ,  H01L2224/05644 ,  H01L2224/05664 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/83102 ,  H01L2224/83191 ,  H01L2224/92225 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06572 ,  H01L2225/06589 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15153 ,  H01L2924/15159 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/15787 ,  H01L2924/15793 ,  H01L2924/16251 ,  H01L2924/16747 ,  H01L2924/014 ,  H01L2924/00014

Abstract: Semiconductor die assemblies and methods of forming the same are described herein. As an example, a semiconductor die assembly may include a thermally conductive casing, a first face of a logic die coupled to the thermally conductive casing to form a thermal path that transfers heat away from the logic die to the thermally conductive casing, a substrate coupled to a second face of the logic die, and a die embedded at least partially in a cavity of the substrate.

公开(公告)号：US09443744B2

公开(公告)日：2016-09-13

申请号：US14330934

申请日：2014-07-14

Applicant: Micron Technology, Inc.

Inventor： Sameer S. Vadhavkar ,  Xiao Li ,  Steven K. Groothuis ,  Jian Li ,  Jaspreet S. Gandhi ,  James M. Derderian ,  David R. Hembree

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L21/56 ,  H01L25/065 ,  H01L25/16 ,  H01L25/00 ,  H01L23/04 ,  H01L21/50 ,  H01L23/36 ,  H01L23/367 ,  H01L21/48

CPC classification number: H01L25/50 ,  H01L21/4882 ,  H01L21/50 ,  H01L21/563 ,  H01L23/04 ,  H01L23/36 ,  H01L23/3675 ,  H01L25/0657 ,  H01L25/16 ,  H01L25/167 ,  H01L2224/16145 ,  H01L2225/06568 ,  H01L2225/06589

Abstract: A semiconductor die assembly having high efficiency thermal paths. In one embodiment, the semiconductor die assembly comprises a package support substrate, a first semiconductor die having a peripheral region and a stacking region, and a second semiconductor die attached to the stacking region of the first die such that the peripheral region is lateral of the second die. The assembly further includes a thermal transfer unit having a base attached to the peripheral region of the first die, a cover attached to the base by an adhesive, and a cavity defined by at least cover, wherein the second die is within the cavity. The assembly also includes an underfill in the cavity, wherein a fillet portion of the underfill extends a distance up along a portion of the footing and upward along at least a portion of the base.

Abstract translation: 具有高效率热路径的半导体管芯组件。 在一个实施例中，半导体管芯组件包括封装支撑衬底，具有周边区域和堆叠区域的第一半导体管芯，以及附接到第一管芯的堆叠区域的第二半导体管芯，使得外围区域是 第二次死亡 组件还包括热传递单元，其具有附接到第一模具的周边区域的基座，通过粘合剂附接到基座的盖子以及至少由盖子限定的空腔，其中第二模具在空腔内。 组件还包括在腔中的底部填充物，其中底部填充物的圆角部分沿着基脚的一部分向上延伸一段距离，并沿基部的至少一部分向上延伸。