公开(公告)号：US20190043817A1

公开(公告)日：2019-02-07

申请号：US16132315

申请日：2018-09-14

Applicant: QUALCOMM Incorporated

Inventor： Manoj KADADE ,  Haiyong XU ,  Ruey Kae ZANG ,  Yue LI ,  Xiaonan ZHANG ,  Christine HAU-RIEGE

IPC: H01L23/00

Abstract: The present disclosure provides packages and methods for fabricating packages. A package may comprise a wafer-level package (WLP) layer comprising a WLP contact and a component within the WLP layer associated with a component depth. A conductive pillar is disposed on the WLP contact and comprises an opposite surface that forms an array pad. The package further comprises a mold over the WLP layer and at least partially surrounding the conductive pillar, wherein the mold compound and the array pad form a substantially planar land grid array (LGA) contact surface that is configured to couple the package to a land grid array. The LGA contact surface has a height that is equal to a selected LGA component height, and the selected LGA component height is equal to a difference between a keepout distance associated with a characteristic of the component within the WLP layer and the component depth.

公开(公告)号：US20150364438A1

公开(公告)日：2015-12-17

申请号：US14303465

申请日：2014-06-12

Applicant: QUALCOMM Incorporated

Inventor： Haiyong XU ,  Manoj Ashok KAKADE ,  Hua GUAN ,  Yue LI ,  Xiaoming CHEN ,  Ruey Kae ZANG

IPC: H01L23/00 ,  B23K3/06

CPC classification number: H01L24/14 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/50 ,  H01L24/11 ,  H01L24/75 ,  H01L2224/1412 ,  H01L2924/15311 ,  H01L2924/301

Abstract: Methods and apparatuses for balancing current delivery. The method couples a low resistance portion of a ball grid array (BGA) to an input portion by at least two vias forming a three-dimensional section. The method couples at least one ball of the BGA to the low resistance portion over a narrow trace.

Abstract translation: 用于平衡当前交付的方法和装置。 该方法通过形成三维截面的至少两个通孔将球栅阵列（BGA）的低电阻部分耦合到输入部分。 该方法将BGA中的至少一个球与窄电阻部分连接。

公开(公告)号：US20180053740A1

公开(公告)日：2018-02-22

申请号：US15243923

申请日：2016-08-22

Applicant: QUALCOMM Incorporated

Inventor： Manoj KAKADE ,  Haiyong XU ,  Ruey Kae ZANG ,  Yue LI ,  Xiaonan ZHANG ,  Christine HAU-RIEGE

IPC: H01L23/00

CPC classification number: H01L24/05 ,  H01L24/03 ,  H01L24/06 ,  H01L24/19 ,  H01L24/20 ,  H01L2224/02373 ,  H01L2224/02379 ,  H01L2224/0239 ,  H01L2224/024 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05024 ,  H01L2224/05124 ,  H01L2224/05552 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05571 ,  H01L2224/0603 ,  H01L2224/06051 ,  H01L2224/12105 ,  H01L2224/13147 ,  H01L2924/07025 ,  H01L2924/1206 ,  H01L2924/15313 ,  H05K1/111 ,  H05K1/185 ,  H05K2201/09472

Abstract: The present disclosure provides packages and methods for fabricating packages. A package may comprise a wafer-level package (WLP) layer comprising first and second WLP contacts and first and second conductive pillars disposed on the first and second WLP contacts. Each conductive pillar may comprise a surface opposite the WLP contact that forms an array pad. The array pads may have different sizes. The package may further comprise a mold over the WLP layer and at least partially surrounding the conductive pillars, wherein the mold compound and the first array pads form a substantially planar LGA contact surface that is configured to couple the package to a land grid array.

公开(公告)号：US20170373032A1

公开(公告)日：2017-12-28

申请号：US15192825

申请日：2016-06-24

Applicant: QUALCOMM Incorporated

Inventor： Jihoon OH ,  Ruey Kae ZANG ,  Lizabeth Ann KESER ,  Reynante Tamunan ALVARADO ,  Haiyong XU ,  Yue LI ,  Steve BEZUK

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/498

CPC classification number: H01L23/49838 ,  H01L21/561 ,  H01L23/3128 ,  H01L23/49822 ,  H01L23/5227 ,  H01L23/5389 ,  H01L24/02 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/96 ,  H01L2224/0233 ,  H01L2224/02331 ,  H01L2224/0235 ,  H01L2224/02372 ,  H01L2224/02373 ,  H01L2224/02375 ,  H01L2224/02379 ,  H01L2224/02381 ,  H01L2224/04105 ,  H01L2224/05111 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/06131 ,  H01L2224/12105 ,  H01L2224/13024 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/14131 ,  H01L2224/1416 ,  H01L2224/14177 ,  H01L2224/96 ,  H01L2924/141 ,  H01L2924/1431 ,  H01L2924/1433 ,  H01L2924/14335 ,  H01L2924/19011 ,  H01L2924/19042 ,  H01L2924/2064 ,  H01L2924/381 ,  H01L2224/03 ,  H01L2224/11

Abstract: Disclosed is a fan-out wafer level packaging (FOWLP) apparatus includes a semiconductor die having at least one input/output (I/O) connection, a first plurality of package balls having a first package ball layout, a first conductive layer forming a first redistribution layer (RDL) and configured to electrically couple to the first plurality of package balls, and a second conductive layer forming a second RDL and including at least one conductive pillar configured to electrically couple the at least one I/O connection of the semiconductor die to the first conductive layer, wherein the second conductive layer enables the semiconductor die to be electrically coupled to a second plurality of package balls having a second package ball layout without a change in position of the at least one I/O connection of the semiconductor die.

公开(公告)号：US20170084594A1

公开(公告)日：2017-03-23

申请号：US14859321

申请日：2015-09-20

Applicant: QUALCOMM Incorporated

Inventor： Jongchil NA ,  Hong Bok WE ,  Ruey Kae ZANG

IPC: H01L25/00 ,  H01L21/56 ,  H01L25/065

CPC classification number: H01L25/50 ,  H01L21/4846 ,  H01L21/563 ,  H01L21/568 ,  H01L23/13 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/16 ,  H01L24/96 ,  H01L25/0657 ,  H01L2224/04105 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06548 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15311

Abstract: A die can be mounted on an already made pattern. Thereafter, substrate and other metal layers can be provided so as to embed the die in the substrate. This avoids the need to form a cavity in the substrate for die placement prevalent in conventional die embedding processes. As a result, die embedding process can be simplified. Also, die misalignment can be reduced or eliminated.