中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

228 records (took 0.03 seconds)

    Memory modules and systems with variable-width data ranks and configurable data-rank timing
    2.
    发明授权
    Memory modules and systems with variable-width data ranks and configurable data-rank timing 有权

    公开(公告)号：US12210467B2

    公开(公告)日：2025-01-28

    申请号：US18480344

    申请日：2023-10-03

    Applicant: Rambus Inc.

    Inventor： Thomas J. Giovannini ,  John Eric Linstadt ,  Catherine Chen

    IPC: G06F13/16 ,  G06F13/40 ,  G06F13/42

    Abstract: A memory system supports single- and dual-memory-module configurations, both supporting point-to-point communication between a host (e.g., a memory controller) and the memory module or modules. Each memory module includes an address-buffer component, data-buffer components, and two sets of memory dies, each set termed a “timing rank,” that can be accessed independently. The one memory module is configured in a wide mode for the single-memory-module configuration, in which case both timing ranks work together, as a “package rank,” to communicate full-width data. Each of two memory modules are configured in a narrow mode for the dual-memory-module configuration, in which case one timing rank from each memory module communicates data in parallel to appear to the host as single package ranks. The data-buffer components support separate and configurable write and read delays for the different timing ranks on each module to provide read and write leveling within and between memory modules.

    BUFFER CIRCUIT WITH ADAPTIVE REPAIR CAPABILITY
    3.
    发明申请
    BUFFER CIRCUIT WITH ADAPTIVE REPAIR CAPABILITY 有权

    公开(公告)号：US20240420793A1

    公开(公告)日：2024-12-19

    申请号：US18766409

    申请日：2024-07-08

    Applicant: Rambus Inc.

    Inventor： Scott C. Best ,  John Eric Linstadt ,  Paul William Roukema

    IPC: G11C29/44 ,  G11C5/04 ,  G11C11/401 ,  G11C29/00 ,  G11C29/02 ,  G11C29/52

    Abstract: A buffer circuit is disclosed. The buffer circuit includes a command address (C/A) interface to receive an incoming activate (ACT) command and an incoming column address strobe (CAS) command. A first match circuit includes first storage to store failure row address information associated with the memory, and first compare logic. The first compare logic is responsive to the ACT command, to compare incoming row address information to the stored failure row address information. A second match circuit includes second storage to store failure column address information associated with the memory, and second compare logic. The second compare logic is responsive to the CAS command, to compare the incoming column address information to the stored failure column address information. Gating logic maintains a state of a matching row address identified by the first compare logic during the comparison carried out by the second compare logic.

    Nonvolatile physical memory with DRAM cache
    4.
    发明授权
    Nonvolatile physical memory with DRAM cache 有权

    公开(公告)号：US12135645B2

    公开(公告)日：2024-11-05

    申请号：US18203569

    申请日：2023-05-30

    Applicant: Rambus Inc.

    Inventor： Frederick A. Ware ,  John Eric Linstadt ,  Christopher Haywood

    IPC: G06F12/0804 ,  G06F12/12 ,  G11C14/00

    Abstract: A hybrid volatile/non-volatile memory module employs a relatively fast, durable, and expensive dynamic, random-access memory (DRAM) cache to store a subset of data from a larger amount of relatively slow and inexpensive nonvolatile memory (NVM). A module controller prioritizes accesses to the DRAM cache for improved speed performance and to minimize programming cycles to the NVM. Data is first written to the DRAM cache where it can be accessed (written to and read from) without the aid of the NVM. Data is only written to the NVM when that data is evicted from the DRAM cache to make room for additional data. Mapping tables relating NVM addresses to physical addresses are distributed throughout the DRAM cache using cache line bits that are not used for data.

    ENERGY EFFICIENT STORAGE OF ERROR-CORRECTION-DETECTION INFORMATION
    5.
    发明公开
    ENERGY EFFICIENT STORAGE OF ERROR-CORRECTION-DETECTION INFORMATION 审中-公开

    公开(公告)号：US20240354191A1

    公开(公告)日：2024-10-24

    申请号：US18649031

    申请日：2024-04-29

    Applicant: Rambus Inc.

    Inventor： Michael Raymond MILLER ,  Stephen Magee ,  John Eric Linstadt

    IPC: G06F11/10 ,  G06F3/06

    CPC classification number: G06F11/1076 ,  G06F3/0619 ,  G06F3/0625 ,  G06F3/0644 ,  G06F3/0673 ,  G06F11/1048

    Abstract: Data and error correction information may involve accessing multiple data channels (e.g., 8) and one error detection and correction channel concurrently. This technique requires a total of N+1 row requests for each access, where N is the number of data channels (e.g., 8 data row accesses and 1 error detection and correction row access equals 9 row accesses.) A single (or at least less than N) data channel row may be accessed concurrently with a single error detection and correction row. This reduces the number of row requests to two (2)—one for the data and one for the error detection and correction information. Because, row requests consume power, reducing the number of row requests is more power efficient.

    Memory controller partitioning for hybrid memory system
    7.
    发明授权
    Memory controller partitioning for hybrid memory system 有权

    公开(公告)号：US12032845B2

    公开(公告)日：2024-07-09

    申请号：US17505503

    申请日：2021-10-19

    Applicant: Rambus Inc.

    Inventor： Frederick A. Ware ,  John Eric Linstadt

    IPC: G06F3/06

    CPC classification number: G06F3/0644 ,  G06F3/0604 ,  G06F3/0679

    Abstract: A compute system includes an execution unit (e.g. of a CPU) with a memory controller providing access to a hybrid physical memory. The physical memory is “hybrid” in that it combines a cache of relatively fast, durable, and expensive memory (e.g. DRAM) with a larger amount of relatively slow, wear-sensitive, and inexpensive memory (e.g. flash). A hybrid controller component services memory commands from the memory controller component and additionally manages cache fetch and evict operations that keep the cache populated with instructions and data that have a high degree of locality of reference. The memory controller alerts the hybrid controller of available access slots to the cache so that the hybrid controller can use the available access slots for cache fetch and evict operations with minimal interference to the memory controller.

    Partial array refresh timing
    9.
    发明授权
    Partial array refresh timing 有权

    公开(公告)号：US11868619B2

    公开(公告)日：2024-01-09

    申请号：US17785269

    申请日：2020-12-03

    Applicant: Rambus Inc.

    Inventor： Liji Gopalakrishnan ,  Thomas Vogelsang ,  John Eric Linstadt

    IPC: G06F3/06 ,  G11C11/406 ,  G06F13/16

    CPC classification number: G06F3/0613 ,  G06F3/0659 ,  G06F3/0673 ,  G11C11/40622 ,  G06F13/1636

    Abstract: A memory controller combines information about which memory component segments are not being refreshed with the information about which rows are going to be refreshed next, to determine, for the current refresh command, the total number of rows that are going to be refreshed. Based on this total number of rows, the memory controller selects how long to wait after the refresh command before issuing a next subsequent command. When the combination of masked segments and the refresh scheme results in less than the ‘nominal’ number of rows typically refreshed in response to a single refresh command, the waiting period before the next command (e.g., non-refresh command) is issued may be reduced from the ‘nominal’ minimum time period, thereby allowing the next command to be issued earlier.

Patent Agency Ranking