公开(公告)号：US20160379946A1

公开(公告)日：2016-12-29

申请号：US14891319

申请日：2014-11-13

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Kazuyoshi MAEKAWA ,  Yuichi KAWANO

IPC: H01L23/00

CPC classification number: H01L24/02 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/522 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/02166 ,  H01L2224/02181 ,  H01L2224/02185 ,  H01L2224/0219 ,  H01L2224/02331 ,  H01L2224/0235 ,  H01L2224/02373 ,  H01L2224/0239 ,  H01L2224/024 ,  H01L2224/0345 ,  H01L2224/0346 ,  H01L2224/03462 ,  H01L2224/03466 ,  H01L2224/0347 ,  H01L2224/035 ,  H01L2224/03614 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05007 ,  H01L2224/05008 ,  H01L2224/05025 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05157 ,  H01L2224/05164 ,  H01L2224/05166 ,  H01L2224/05176 ,  H01L2224/0518 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05548 ,  H01L2224/05566 ,  H01L2224/05567 ,  H01L2224/05664 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/4502 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45565 ,  H01L2224/45664 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/48664 ,  H01L2224/48864 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/04941 ,  H01L2924/07025 ,  H01L2924/10253 ,  H01L2924/1306 ,  H01L2924/15183 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/01008

Abstract: A semiconductor device includes: a pad electrode 9a formed in an uppermost layer of a plurality of wiring layers; a base insulating film 11 having an opening 11a on the pad electrode 9a; a base metal film UM formed on the base insulating film 11; a redistribution line RM formed on the base metal film UM; and a cap metal film CM formed so as to cover an upper surface and a side surface of the redistribution line RM. In addition, in a region outside the redistribution line RM, the base metal film UM made of a material different from that of the redistribution line RM and the cap metal film CM made of a material different from the redistribution line RM are formed between the cap metal film CM formed on the side surface of the redistribution line RM and the base insulating film 11, and the base metal film UM and the cap metal film CM are in direct contact with each other in the region outside the redistribution line RM.

Abstract translation: 半导体器件包括：形成在多个布线层的最上层中的焊盘电极9a; 在焊盘电极9a上具有开口11a的基底绝缘膜11; 形成在基底绝缘膜11上的贱金属膜UM; 形成在基底金属膜UM上的再分布线RM; 和形成为覆盖再分配线RM的上表面和侧面的帽金属膜CM。 另外，在再分配线RM外部的区域中，由不同于再分配线RM的材料制成的贱金属膜UM和由再分配线RM不同的材料制成的帽金属膜CM形成在盖 形成在再分配线路RM和基底绝缘膜11的侧面上的金属膜CM和基底金属膜UM和盖金属膜CM在再分配线路RM外部的区域中彼此直接接触。

公开(公告)号：US20200035552A1

公开(公告)日：2020-01-30

申请号：US16592869

申请日：2019-10-04

Applicant: Renesas Electronics Corporation

Inventor： Kazuyuki OMORI ,  Seiji MURANAKA ,  Kazuyoshi MAEKAWA

IPC: H01L21/768 ,  H01L23/528 ,  H01L23/532 ,  C23C14/06 ,  C23C14/16 ,  C23C14/34 ,  H01L21/285

Abstract: Performance of a semiconductor device is improved. In one embodiment, for example, deposition time is increased from 4.6 sec to 6.9 sec. In other words, in one embodiment, thickness of a tantalum nitride film is increased by increasing the deposition time. Specifically, in one embodiment, deposition time is increased such that a tantalum nitride film provided on the bottom of a connection hole to be coupled to a wide interconnection has a thickness within a range from 5 to 10 nm.

公开(公告)号：US20170040212A1

公开(公告)日：2017-02-09

申请号：US15298302

申请日：2016-10-20

Applicant: Renesas Electronics Corporation

Inventor： Kazuyuki OMORI ,  Seiji MURANAKA ,  Kazuyoshi MAEKAWA

IPC: H01L21/768 ,  H01L21/285 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L21/76843 ,  C23C14/0641 ,  C23C14/165 ,  C23C14/34 ,  H01L21/2855 ,  H01L21/76802 ,  H01L21/76807 ,  H01L21/7684 ,  H01L21/76846 ,  H01L21/76876 ,  H01L21/76879 ,  H01L21/76897 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/53228 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Performance of a semiconductor device is improved. In one embodiment, for example, deposition time is increased from 4.6 sec to 6.9 sec. In other words, in one embodiment, thickness of a tantalum nitride film is increased by increasing the deposition time. Specifically, in one embodiment, deposition time is increased such that a tantalum nitride film provided on the bottom of a connection hole to be coupled to a wide interconnection has a thickness within a range from 5 to 10 nm.

Abstract translation: 提高了半导体器件的性能。 在一个实施例中，例如，沉积时间从4.6秒增加到6.9秒。 换句话说，在一个实施例中，通过增加沉积时间来增加氮化钽膜的厚度。 具体地，在一个实施例中，沉积时间增加，使得设置在要连接到宽互连件的连接孔的底部上的氮化钽膜具有在5至10nm的范围内的厚度。

公开(公告)号：US20140141560A1

公开(公告)日：2014-05-22

申请号：US14082976

申请日：2013-11-18

Applicant: Renesas Electronics Corporation

Inventor： Kazuyoshi MAEKAWA

IPC: H01L27/146

CPC classification number: H01L27/14689 ,  H01L27/14632 ,  H01L27/14634 ,  H01L27/1464 ,  H01L27/14687 ,  H01L27/1469

Abstract: Disclosed is a manufacturing method of a semiconductor device including a step of attaching semiconductor wafers together, in which it is prevented that the bonding strength between the attached semiconductor wafers may be decreased due to a void caused between the two semiconductor wafers. Moisture, etc., adsorbed to the surfaces of the semiconductor wafers is desorbed by performing a heat treatment on the semiconductor wafers after cleaning the surfaces thereof with pure water. Subsequently, after a plasma treatment is performed on the semiconductor wafers, the two semiconductor wafers are attached together. The wafers are firmly bonded together by subjecting to a high-temperature heat treatment.

Abstract translation: 公开了一种半导体器件的制造方法，其包括将半导体晶片连接在一起的步骤，其中可以防止由于在两个半导体晶片之间引起的空隙而导致的附接半导体晶片之间的结合强度降低。 吸附到半导体晶片的表面的水分等通过在用纯水清洁其表面之后对半导体晶片进行热处理来解吸。 随后，在对半导体晶片进行等离子体处理之后，将两个半导体晶片连接在一起。 通过进行高温热处理将晶片牢固地结合在一起。

公开(公告)号：US20220384257A1

公开(公告)日：2022-12-01

申请号：US17887045

申请日：2022-08-12

Applicant: Renesas Electronics Corporation

Inventor： Kazuyuki OMORI ,  Seiji MURANAKA ,  Kazuyoshi MAEKAWA

IPC: H01L21/768 ,  H01L23/528 ,  H01L23/532 ,  C23C14/06 ,  C23C14/16 ,  C23C14/34 ,  H01L21/285

Abstract: Performance of a semiconductor device is improved. In one embodiment, for example, deposition time is increased from 4.6 sec to 6.9 sec. In other words, in one embodiment, thickness of a tantalum nitride film is increased by increasing the deposition time. Specifically, in one embodiment, deposition time is increased such that a tantalum nitride film provided on the bottom of a connection hole to be coupled to a wide interconnection has a thickness within a range from 5 to 10 nm.

公开(公告)号：US20160043133A1

公开(公告)日：2016-02-11

申请号：US14797099

申请日：2015-07-11

Applicant: Renesas Electronics Corporation

Inventor： Kazuyoshi MAEKAWA

IPC: H01L27/146

CPC classification number: H01L27/14687 ,  H01L27/14621 ,  H01L27/14623 ,  H01L27/14627 ,  H01L27/14636 ,  H01L27/1464 ,  H01L27/14645 ,  H01L27/14685

Abstract: A solid-state imaging element has problems of occurrence of dark current due to influences of an interface state at an interface between a semiconductor and an insulating film, e.g., between silicon and silicon oxide, and of charges generated in a device manufacturing process, which leads to signal noise, thereby degrading the function of a device, specifically, the imaging quality. The outline of the invention in the present application relates to a manufacturing method of a semiconductor integrated circuit device with a surface-irradiation type image sensor, which includes irradiating a main surface of a semiconductor wafer with photodiodes formed therein, with far-ultraviolet ray after forming a lowermost wiring layer of a multi-layer wiring and before forming a color filter layer, and then applying a heat treatment to the wafer.

Abstract translation: 固态成像元件由于半导体和绝缘膜之间的界面（例如硅和氧化硅之间）和在器件制造过程中产生的电荷的界面状态的影响而产生暗电流的问题，其中 导致信号噪声，从而降低设备的功能，特别是成像质量。 本申请的发明内容涉及一种具有表面照射型图像传感器的半导体集成电路器件的制造方法，该半导体集成电路器件包括用形成于其中的光电二极管照射半导体晶片的主表面的远紫外线 形成多层布线的最下布线层，然后形成滤色器层，然后对晶片进行热处理。

公开(公告)号：US20180240700A1

公开(公告)日：2018-08-23

申请号：US15953948

申请日：2018-04-16

Applicant: Renesas Electronics Corporation

Inventor： Kazuyuki OMORI ,  Seiji MURANAKA ,  Kazuyoshi MAEKAWA

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/528 ,  C23C14/06 ,  H01L21/285 ,  C23C14/16 ,  C23C14/34

CPC classification number: H01L21/76843 ,  C23C14/0641 ,  C23C14/165 ,  C23C14/34 ,  H01L21/2855 ,  H01L21/76802 ,  H01L21/76807 ,  H01L21/7684 ,  H01L21/76846 ,  H01L21/76876 ,  H01L21/76879 ,  H01L21/76897 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/53228 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Performance of a semiconductor device is improved. In one embodiment, for example, deposition time is increased from 4.6 sec to 6.9 sec. In other words, in one embodiment, thickness of a tantalum nitride film is increased by increasing the deposition time. Specifically, in one embodiment, deposition time is increased such that a tantalum nitride film provided on the bottom of a connection hole to be coupled to a wide interconnection has a thickness within a range from 5 to 10 nm.

公开(公告)号：US20160181184A1

公开(公告)日：2016-06-23

申请号：US14943900

申请日：2015-11-17

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Masahiro MATSUMOTO ,  Kazuyoshi MAEKAWA ,  Yuichi KAWANO

IPC: H01L23/495 ,  H01L21/48

CPC classification number: H01L21/4817 ,  H01L21/76852 ,  H01L23/3121 ,  H01L23/525 ,  H01L23/53238 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/45 ,  H01L24/48 ,  H01L2221/1078 ,  H01L2224/02166 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05007 ,  H01L2224/05008 ,  H01L2224/05075 ,  H01L2224/05548 ,  H01L2224/05664 ,  H01L2224/0612 ,  H01L2224/131 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45565 ,  H01L2224/45644 ,  H01L2224/45664 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2924/014 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/00

Abstract: The present invention makes it possible to improve the reliability of a semiconductor device. The semiconductor device has, over a semiconductor substrate, a pad electrode formed at the uppermost layer of a plurality of wiring layers, a surface protective film having an opening over the pad electrode, a redistribution line being formed over the surface protective film and having an upper surface and a side surface, a sidewall barrier film comprising an insulating film covering the side surface and exposing the upper surface of the redistribution line, and a cap metallic film covering the upper surface of the redistribution line. Then the upper surface and side surface of the redistribution line are covered with the cap metallic film or the sidewall barrier film and the cap metallic film and the sidewall barrier film have an overlapping section.

Abstract translation: 本发明使得可以提高半导体器件的可靠性。 半导体器件在半导体衬底上具有形成在多个布线层的最上层的焊盘电极，在焊盘电极上具有开口的表面保护膜，在该表面保护膜上形成再分配线，并具有 上表面和侧表面，侧壁阻挡膜，其包括覆盖侧表面并暴露再分布线的上表面的绝缘膜，以及覆盖再分布线的上表面的帽金属膜。 然后再分配线的上表面和侧表面被盖金属膜或侧壁阻挡膜覆盖，并且帽金属膜和侧壁阻挡膜具有重叠部分。

公开(公告)号：US20160118437A1

公开(公告)日：2016-04-28

申请号：US14987035

申请日：2016-01-04

Applicant: Renesas Electronics Corporation

Inventor： Kazuyoshi MAEKAWA

IPC: H01L27/146

CPC classification number: H01L27/14689 ,  H01L27/14632 ,  H01L27/14634 ,  H01L27/1464 ,  H01L27/14687 ,  H01L27/1469

Abstract: Disclosed is a manufacturing method of a semiconductor device including a step of attaching semiconductor wafers together, in which it is prevented that the bonding strength between the attached semiconductor wafers may be decreased due to a void caused between the two semiconductor wafers. Moisture, etc., adsorbed to the surfaces of the semiconductor wafers is desorbed by performing a heat treatment on the semiconductor wafers after cleaning the surfaces thereof with pure water. Subsequently, after a plasma treatment is performed on the semiconductor wafers, the two semiconductor wafers are attached together. The wafers are firmly bonded together by subjecting to a high-temperature heat treatment.

Abstract translation: 公开了一种半导体器件的制造方法，其包括将半导体晶片连接在一起的步骤，其中可以防止由于在两个半导体晶片之间引起的空隙而导致的附接半导体晶片之间的结合强度降低。 吸附到半导体晶片的表面的水分等通过在用纯水清洁其表面之后对半导体晶片进行热处理来解吸。 随后，在对半导体晶片进行等离子体处理之后，将两个半导体晶片连接在一起。 通过进行高温热处理将晶片牢固地结合在一起。

公开(公告)号：US20230097408A1

公开(公告)日：2023-03-30

申请号：US17489145

申请日：2021-09-29

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Nozomi ITO ,  Kazuyoshi MAEKAWA ,  Yuji TAKAHASHI ,  Yasuaki TSUCHIYA ,  Nobuhito SHIRAISHI

IPC: H01L49/02 ,  H01L23/522 ,  H01C7/00 ,  H01C17/12

Abstract: A semiconductor device includes an insulating layer, a first conductive film, a second conductive film and a thin-film resistor. The insulating layer has a penetrating portion. The first conductive film is formed in the penetrating portion such that a recess is formed at an upper part of the penetration portion. The second conductive film is formed on an upper surface of the first conductive film and an inner surface of the penetrating portion. The thin-film resistor includes silicon and metal. The thin-film resistor is formed on the second conductive film and the insulating layer.