公开(公告)号：US20230037374A1

公开(公告)日：2023-02-09

申请号：US17847984

申请日：2022-06-23

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Tatsuyoshi MIHARA

IPC: H01L27/11597 ,  H01L27/11587

Abstract: A semiconductor device includes a plurality of word lines extending in a first direction in a plan view, a plurality of bit lines extending in a second direction orthogonal to the first direction in a plan view, and a plurality of memory cells arranged in matrix in the first direction and the second direction. The memory cell includes a gate insulating film, a lower layer electrode, a ferroelectric film, an upper layer electrode, and a pair of semiconductor regions, and a first width of the lower layer electrode in the first direction is larger than a second width of the upper layer electrode in the first direction in a plan view.

公开(公告)号：US20170278938A1

公开(公告)日：2017-09-28

申请号：US15512475

申请日：2015-03-30

Applicant: Renesas Electronics Corporation

Inventor： Tatsuyoshi MIHARA

IPC: H01L29/423 ,  H01L21/28 ,  H01L21/3213 ,  H01L21/02 ,  H01L21/306 ,  H01L21/311 ,  H01L21/308 ,  H01L27/11568 ,  H01L29/06

CPC classification number: H01L29/42344 ,  H01L21/02233 ,  H01L21/28282 ,  H01L21/30604 ,  H01L21/3086 ,  H01L21/31111 ,  H01L21/3213 ,  H01L27/11568 ,  H01L27/1157 ,  H01L29/0684 ,  H01L29/4238 ,  H01L29/66833 ,  H01L29/792

Abstract: A semiconductor substrate (1) includes a region (AR3) between a region (AR1) and a region (AR2), a control gate electrode (CG) is formed on an upper surface (TS1) of the region (AR1), and a memory gate electrode (MG) is formed on an upper surface (TS2) of the region (AR2). The upper surface (TS2) is lower than the upper surface (TS1), and the region (AR3) has a connection surface (TS3) connecting the upper surface (TS1) and the upper surface (TS2). An end (EP1) of the connection surface (TS3) which is on the upper surface (TS2) side is arranged closer to the memory gate electrode (MG) than an end (EP2) of the connection surface (TS3) which is on the upper surface (TS1) side, and is arranged lower than the end (EP2).

公开(公告)号：US20170271162A1

公开(公告)日：2017-09-21

申请号：US15404463

申请日：2017-01-12

Applicant: Renesas Electronics Corporation

Inventor： Tamotsu OGATA ,  Tatsuyoshi MIHARA

IPC: H01L21/28 ,  H01L29/423 ,  H01L21/311 ,  H01L29/792 ,  H01L21/3105 ,  H01L27/1157 ,  H01L29/66

CPC classification number: H01L21/28282 ,  H01L21/31051 ,  H01L21/31105 ,  H01L21/31144 ,  H01L27/1157 ,  H01L27/11573 ,  H01L29/42344 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66833 ,  H01L29/792

Abstract: Over a semiconductor substrate, a memory gate electrode for a nonvolatile memory cell is formed via a first insulating film having an internal charge storage portion. A dummy control gate electrode is formed so as to be adjacent to the memory gate electrode via a second insulating film. The memory and the dummy control gate electrodes are made of different materials. A third insulating film is formed so as to cover the memory and the dummy control gate electrodes and then polished to expose the memory and the dummy control gate electrodes. Then, etching is performed under a condition in which the memory gate electrode is less likely to be etched than the dummy control gate electrode to remove the dummy control gate electrode. Then, in a trench as a region from which the dummy control gate electrode is removed, a control gate electrode for the memory cell is formed.

公开(公告)号：US20170207128A1

公开(公告)日：2017-07-20

申请号：US15473699

申请日：2017-03-30

Applicant: Renesas Electronics Corporation

Inventor： Koji MAEKAWA ,  Tatsuyoshi MIHARA

IPC: H01L21/8234 ,  H01L29/36 ,  H01L21/266 ,  H01L29/06 ,  H01L21/311 ,  H01L29/66

CPC classification number: H01L21/823468 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/31116 ,  H01L21/823418 ,  H01L21/823462 ,  H01L29/0615 ,  H01L29/36 ,  H01L29/66477 ,  H01L29/6653 ,  H01L29/66553 ,  Y10S257/90 ,  Y10S438/90

Abstract: An insulating film and another insulating film are formed over a semiconductor substrate in that order to cover first, second, and third gate electrodes. The another insulating film is etched back to form sidewall spacers over side surfaces of the insulating film. Then, the sidewall spacers over the side surfaces of the insulating films corresponding to the sidewalls of the first and second gate electrodes are removed to leave the sidewall spacers over the side surfaces of the insulating film corresponding to the sidewalls of the third gate electrode. Then, the sidewall spacers and the insulating films are etched back, so that the sidewall spacers are formed of the insulating film over the sidewalls of the first, second, and third gate electrodes.

公开(公告)号：US20140361361A1

公开(公告)日：2014-12-11

申请号：US14466092

申请日：2014-08-22

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Tatsuyoshi MIHARA

IPC: H01L29/792 ,  G11C11/56 ,  H01L27/11 ,  G11C16/04

CPC classification number: H01L27/0629 ,  G11C11/5671 ,  G11C16/0466 ,  G11C16/0475 ,  H01L21/823468 ,  H01L27/1104 ,  H01L27/11565 ,  H01L27/11568 ,  H01L29/4234 ,  H01L29/66545 ,  H01L29/66833 ,  H01L29/792

Abstract: The improvement of the reliability of a semiconductor device having a split gate type MONOS memory is implemented. An ONO film and a second polysilicon film are sequentially formed so as to fill between a first polysilicon film and a dummy gate electrode. Then, the dummy gate electrode is removed. Then, the top surfaces of the first and second polysilicon films are polished, thereby to form a memory gate electrode formed of the second polysilicon film at the sidewall of a control gate electrode formed of the first polysilicon film via the ONO film. As a result, the memory gate electrode high in perpendicularity of the sidewall, and uniform in film thickness is formed.

公开(公告)号：US20210111256A1

公开(公告)日：2021-04-15

申请号：US16601234

申请日：2019-10-14

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Naoki TAKIZAWA ,  Tatsuyoshi MIHARA

IPC: H01L21/28 ,  H01L27/11573 ,  H01L27/1157 ,  H01L29/66

Abstract: After the step of polishing, a part of each of each gate electrode is removed such that the upper surface of each gate electrode is located closer than the damaged region formed in the gate insulating film located between the gate electrodes to the main surface of the semiconductor substrate in cross-section view. Thus, it is possible to suppress the occurrence of a short-circuit defect during the operation of the semiconductor device.

公开(公告)号：US20190006353A1

公开(公告)日：2019-01-03

申请号：US16125857

申请日：2018-09-10

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Tatsuyoshi MIHARA

IPC: H01L27/06 ,  H01L29/792 ,  H01L29/66 ,  H01L29/423 ,  H01L27/11568 ,  G11C11/56 ,  H01L27/11 ,  H01L27/11565 ,  G11C16/04 ,  H01L21/8234

Abstract: The improvement of the reliability of a semiconductor device having a split gate type MONOS memory is implemented. An ONO film and a second polysilicon film are sequentially formed so as to fill between a first polysilicon film and a dummy gate electrode. Then, the dummy gate electrode is removed. Then, the top surfaces of the first and second polysilicon films are polished, thereby to form a memory gate electrode formed of the second polysilicon film at the sidewall of a control gate electrode formed of the first polysilicon film via the ONO film. As a result, the memory gate electrode high in perpendicularity of the sidewall, and uniform in film thickness is formed.

公开(公告)号：US20180233414A1

公开(公告)日：2018-08-16

申请号：US15950688

申请日：2018-04-11

Applicant: Renesas Electronics Corporation

Inventor： Koji MAEKAWA ,  Tatsuyoshi MIHARA

IPC: H01L21/8234 ,  H01L29/06 ,  H01L21/266 ,  H01L21/311 ,  H01L29/36 ,  H01L29/66

CPC classification number: H01L21/823468 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/31116 ,  H01L21/823418 ,  H01L21/823462 ,  H01L29/0615 ,  H01L29/36 ,  H01L29/66477 ,  H01L29/6653 ,  H01L29/66553 ,  Y10S257/90 ,  Y10S438/90

Abstract: An insulating film and another insulating film are formed over a semiconductor substrate in that order to cover first, second, and third gate electrodes. The another insulating film is etched back to form sidewall spacers over side surfaces of the insulating film. Then, the sidewall spacers over the side surfaces of the insulating films corresponding to the sidewalls of the first and second gate electrodes are removed to leave the sidewall spacers over the side surfaces of the insulating film corresponding to the sidewalls of the third gate electrode. Then, the sidewall spacers and the insulating films are etched back, so that the sidewall spacers are formed of the insulating film over the sidewalls of the first, second, and third gate electrodes.

公开(公告)号：US20180006048A1

公开(公告)日：2018-01-04

申请号：US15691136

申请日：2017-08-30

Applicant: Renesas Electronics Corporation

Inventor： Keisuke TSUKAMOTO ,  Tatsuyoshi MIHARA

IPC: H01L27/11531 ,  H01L21/28 ,  H01L21/283 ,  H01L21/285 ,  H01L21/3105 ,  H01L21/265 ,  H01L29/66 ,  H01L29/49 ,  H01L29/45 ,  H01L29/423 ,  H01L27/11573 ,  H01L27/11568 ,  H01L27/11563 ,  H01L27/11521 ,  H01L21/324 ,  H01L21/3213 ,  H01L21/3205 ,  H01L21/311 ,  H01L29/788 ,  H01L29/51

CPC classification number: H01L27/11531 ,  H01L21/265 ,  H01L21/28202 ,  H01L21/28282 ,  H01L21/283 ,  H01L21/28518 ,  H01L21/31053 ,  H01L21/31111 ,  H01L21/32053 ,  H01L21/32133 ,  H01L21/324 ,  H01L27/11521 ,  H01L27/11563 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/42324 ,  H01L29/45 ,  H01L29/4916 ,  H01L29/495 ,  H01L29/513 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66507 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/66825 ,  H01L29/7881 ,  Y10S438/926

Abstract: A control gate electrode and a memory gate electrode of a memory cell of a non-volatile memory are formed in a memory cell region of a semiconductor substrate, and a dummy gate electrode is formed in a peripheral circuit region. Then, n+-type semiconductor regions for a source or a drain of the memory cell are formed in the memory cell region and n+-type semiconductor regions for a source or a drain of MISFET are formed in the peripheral circuit region. Then, a metal silicide layer is formed over the n+-type semiconductor regions but the metal silicide layer is not formed over the control gate electrode, the memory gate electrode, and the gate electrode. Subsequently, the gate electrode is removed and replaced with the gate electrode for MISFET, Then, after removing the gate electrode and replacing it with a gate electrode for MISFET, a metal silicide layer is formed over the memory gate electrode and the control gate electrode.

公开(公告)号：US20160293719A1

公开(公告)日：2016-10-06

申请号：US15061870

申请日：2016-03-04

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Tatsuyoshi MIHARA

IPC: H01L29/423 ,  H01L23/522 ,  H01L21/285 ,  H01L27/115 ,  H01L21/28

CPC classification number: H01L21/28282 ,  H01L27/1157 ,  H01L27/11573 ,  H01L29/42344

Abstract: A semiconductor device includes a control gate electrode and a memory gate electrode which are formed over the main surface of a semiconductor substrate in a memory cell region, and a first electrode and a second electrode which are formed over the main surface of the semiconductor substrate in a shunt region. The first electrode is formed integrally with the control gate electrode, and the second electrode is formed integrally with the memory gate electrode. The second electrode includes a first section formed along the side wall of the first electrode, and a second section extending along the main surface of the semiconductor substrate. Also, the height of the upper surface of the first electrode with respect to the main surface of the semiconductor substrate is generally same to the height of the upper surface of the first section of the second electrode.

Abstract translation: 半导体器件包括在存储单元区域中形成在半导体衬底的主表面上的控制栅电极和存储栅电极，以及形成在半导体衬底的主表面上的第一电极和第二电极 一个分流区域。 第一电极与控制栅电极整体形成，第二电极与存储栅电极一体形成。 第二电极包括沿着第一电极的侧壁形成的第一部分和沿半导体衬底的主表面延伸的第二部分。 此外，第一电极的上表面相对于半导体衬底的主表面的高度通常与第二电极的第一部分的上表面的高度相同。