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    THREE-DIMENSIONAL MEMORY DEVICE INCLUDING SELF-ALIGNED DIELECTRIC ISOLATION REGIONS FOR CONNECTION VIA STRUCTURES AND METHOD OF MAKING THE SAME
    3.
    发明申请
    THREE-DIMENSIONAL MEMORY DEVICE INCLUDING SELF-ALIGNED DIELECTRIC ISOLATION REGIONS FOR CONNECTION VIA STRUCTURES AND METHOD OF MAKING THE SAME 有权

    公开(公告)号：US20210028111A1

    公开(公告)日：2021-01-28

    申请号：US16519260

    申请日：2019-07-23

    Applicant: SANDISK TECHNOLOGIES LLC

    Inventor： James KAI ,  Johann Alsmeier ,  Jixin YU

    IPC: H01L23/535 ,  H01L27/11556 ,  H01L27/11582 ,  H01L23/522 ,  H01L21/768

    Abstract: A vertically alternating sequence of continuous insulating layers and continuous sacrificial material layers is formed over a substrate. Memory stack structures are formed through the vertically alternating sequence. The vertically alternating sequence is divided into alternating stacks of insulating layers and sacrificial material layers by forming backside trenches therethrough. Each neighboring pair of alternating stacks is laterally spaced apart from each other by a respective backside trench. The sacrificial material layers are replaced with multipart layers. Each multipart layer includes a respective electrically conductive layer that laterally extends continuously between a respective neighboring pair of backside trenches and at least one dielectric material plate that is a remaining portion of a sacrificial material layer, is laterally enclosed by the respective electrically conductive layer, and is laterally spaced from a most proximal one of the backside trenches by a uniform lateral offset distance.

    THROUGH-ARRAY CONDUCTIVE VIA STRUCTURES FOR A THREE-DIMENSIONAL MEMORY DEVICE AND METHODS OF MAKING THE SAME
    4.
    发明申请
    THROUGH-ARRAY CONDUCTIVE VIA STRUCTURES FOR A THREE-DIMENSIONAL MEMORY DEVICE AND METHODS OF MAKING THE SAME 审中-公开

    公开(公告)号：US20200235120A1

    公开(公告)日：2020-07-23

    申请号：US16251863

    申请日：2019-01-18

    Applicant: SANDISK TECHNOLOGIES LLC

    Inventor： James KAI ,  Murshed CHOWDHURY ,  Fumiaki TOYAMA ,  Johann ALSMEIER ,  Masaaki HIGASHITANI

    IPC: H01L27/11582 ,  H01L27/11573 ,  H01L27/1157 ,  H01L27/11565 ,  H01L23/522 ,  H01L23/528 ,  H01L21/28

    Abstract: An alternating stack of insulating layers and dielectric spacer layers is formed over a semiconductor substrate. Memory stack structures are formed through the alternating stack. Backside trenches, a moat trench, and a contact opening are formed through the alternating stack, and are subsequently filled with sacrificial backside trench fill material structures, a sacrificial moat trench fill structure, and a sacrificial contact opening fill structure, respectively. The sacrificial moat trench fill structure is replaced with tubular dielectric wall structure. Portions of the dielectric spacer layers located outside the tubular dielectric wall structure are replaced with electrically conductive layers. The sacrificial backside trench fill material structures are replaced with backside trench fill structures. The sacrificial contact opening fill structure is replaced with a conductive via structure. Concurrent formation of the backside trenches, the moat trench, and the contact opening reduces processing steps and cost.

    THREE-DIMENSIONAL MEMORY DEVICE HAVING ON-PITCH DRAIN SELECT GATE ELECTRODES AND METHOD OF MAKING THE SAME
    8.
    发明申请
    THREE-DIMENSIONAL MEMORY DEVICE HAVING ON-PITCH DRAIN SELECT GATE ELECTRODES AND METHOD OF MAKING THE SAME 审中-公开

    公开(公告)号：US20190267391A1

    公开(公告)日：2019-08-29

    申请号：US16406283

    申请日：2019-05-08

    Applicant: SANDISK TECHNOLOGIES LLC

    Inventor： Muneyuki IMAI ,  James KAI

    IPC: H01L27/11556 ,  H01L21/28 ,  H01L27/11582 ,  H01L29/06 ,  G11C5/02 ,  G11C16/04

    Abstract: An array of memory stack structures extends through an alternating stack of insulating layers and electrically conductive layers. The drain-select-level assemblies may be provided by forming drain-select-level openings through a drain-select-level sacrificial material layer, and by forming a combination of a cylindrical electrode portion and a first gate dielectric mayin each first drain-select-level opening while forming a second gate dielectric directly on a sidewall of each second drain-select-level opening in a second subset of the drain-select-level openings. A strip electrode portion is formed by replacing the drain-select-level sacrificial material layer with a conductive material. Structures filling the second subset of the drain-select-level openings may be used as dummy structures at a periphery of an array. The dummy structures are free of gate electrodes and thus prevents a leakage current therethrough.

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