公开(公告)号：US11935867B2

公开(公告)日：2024-03-19

申请号：US17398406

申请日：2021-08-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yanggyoo Jung ,  Sungeun Kim ,  Sangmin Yong ,  Hae-Jung Yu

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/538 ,  H01L23/64

CPC classification number: H01L25/0652 ,  H01L23/5383 ,  H01L23/642 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2924/3511

Abstract: A semiconductor package comprising a package substrate that extends in a first direction and a second direction perpendicular to the first direction, a plurality of logic dies and a memory stack structure on the package substrate, and an interposer substrate mounted in the package substrate. The memory stack structure vertically overlaps the interposer substrate. Each of the logic dies includes a first part that is horizontally offset from the interposer substrate and a second part that vertically overlaps the interposer substrate. The interposer substrate includes an interlayer dielectric layer and a plurality of wiring lines in the interlayer dielectric layer. The memory stack structure is electrically connected to at least one of the logic dies through the wiring lines of the interposer substrate.

公开(公告)号：US09054228B2

公开(公告)日：2015-06-09

申请号：US14160008

申请日：2014-01-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eun-Kyoung Choi ,  Jong-Youn Kim ,  Sang-Wook Park ,  Hae-Jung Yu ,  In-Young Lee ,  Sang-Uk Han ,  Ji-Seok Hong

IPC: H01L23/02 ,  H01L23/34 ,  H01L23/00 ,  H01L23/36 ,  H01L23/373 ,  H01L23/433 ,  H01L23/48 ,  H01L23/31 ,  H01L21/56

CPC classification number: H01L24/97 ,  H01L21/561 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/36 ,  H01L23/3737 ,  H01L23/4334 ,  H01L23/481 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06568 ,  H01L2225/06589 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00

Abstract: Semiconductor packages including a heat spreader and methods of forming the same are provided. The semiconductor packages may include a first semiconductor chip, a second semiconductor chip, and a heat spreader stacked sequentially. The semiconductor packages may also include a thermal interface material (TIM) layer surrounding the second semiconductor chip and directly contacting a sidewall of the second semiconductor chip. An upper surface of the TIM layer may directly contact a lower surface of the heat spreader, and a sidewall of the TIM layer may be substantially coplanar with a sidewall of the heat spreader. In some embodiments, a sidewall of the first semiconductor chip may be substantially coplanar with the sidewall of the TIM layer.

Abstract translation: 提供了包括散热器的半导体封装及其形成方法。 半导体封装可以包括顺序堆叠的第一半导体芯片，第二半导体芯片和散热器。 半导体封装还可以包括围绕第二半导体芯片并直接接触第二半导体芯片的侧壁的热界面材料（TIM）层。 TIM层的上表面可以直接接触散热器的下表面，并且TIM层的侧壁可以与散热器的侧壁基本上共面。 在一些实施例中，第一半导体芯片的侧壁可以与TIM层的侧壁基本共面。

公开(公告)号：US11282792B2

公开(公告)日：2022-03-22

申请号：US16805890

申请日：2020-03-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young Kun Jee ,  Hae-Jung Yu ,  Sangwon Kim ,  Un-Byoung Kang ,  Jongho Lee ,  Dae-Woo Kim ,  Wonjae Lee

IPC: H01L23/538 ,  H01L25/18 ,  H01L23/498

Abstract: A semiconductor package includes a package substrate, a plurality of package terminals disposed on the bottom surface of the package substrate, and an interposer substrate disposed on the top surface of the package substrate, a plurality of interposer terminals disposed on the bottom surface of the interposer substrate and electrically connected to the package substrate, a first semiconductor chip disposed on the top surface of the interposer substrate, a second semiconductor chip disposed on the top surface of the interposer substrate and disposed to be horizontally separated from the first semiconductor chip, a first plurality of signal pads disposed on the top surface of the interposer substrate and electrically connected to wiring in the interposer substrate and one or more circuits in the first semiconductor chip, a second plurality of signal pads disposed on the top surface of the interposer substrate and electrically connected to wiring in the interposer substrate and to one or more circuits in the second semiconductor chip, and a plurality of dummy pads disposed outside of an area occupied by the first semiconductor chip or the second semiconductor chip from a top-down view and disposed on the top surface of the interposer substrate. Each pad of the first plurality of signal pads and the second plurality of signal pads is configured to transfer signals between the interposer substrate and a respective semiconductor chip, and each pad of the dummy pads is not configured to transfer signals between the interposer substrate and any semiconductor chip disposed thereon.

公开(公告)号：US08912048B2

公开(公告)日：2014-12-16

申请号：US13803662

申请日：2013-03-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jong-Youn Kim ,  Ji-Hwang Kim ,  Hae-Jung Yu ,  Cha-Jea Jo

IPC: H01L21/00 ,  H01L21/82

CPC classification number: H01L21/82 ,  H01L21/561 ,  H01L21/568 ,  H01L21/78 ,  H01L23/3135 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/92 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/03002 ,  H01L2224/03009 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/11009 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/92125 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06568 ,  H01L2225/06589 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/10328 ,  H01L2924/10329 ,  H01L2924/10332 ,  H01L2924/10333 ,  H01L2924/10335 ,  H01L2924/10523 ,  H01L2924/12042 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/1438 ,  H01L2924/15311 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2224/32225 ,  H01L2224/05552 ,  H01L2924/00

Abstract: A method of fabricating a semiconductor device includes attaching a semiconductor substrate to a carrier using a carrier fixing layer, where the semiconductor substrate including a plurality of semiconductor chips. The method further includes forming gaps between adjacent ones of the chips. The gaps may be formed using one or more chemicals or light which act to remove portions of the semiconductor substrate to expose the carrier fixing layer. Additional portions of the carrier fixing layer are then removed to allow for removal of the chips from the carrier.

Abstract translation: 制造半导体器件的方法包括：使用载体固定层将半导体衬底附着到载体上，其中半导体衬底包括多个半导体芯片。 该方法还包括在相邻芯片之间形成间隙。 可以使用一种或多种化学品或光来形成间隙，所述化学物质或光用于去除半导体衬底的部分以暴露载体固定层。 然后移除载体固定层的附加部分以允许将芯片从载体上移除。

公开(公告)号：US12080676B2

公开(公告)日：2024-09-03

申请号：US17646672

申请日：2021-12-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hae-Jung Yu

IPC: H01L23/31 ,  H01L23/00 ,  H01L23/48 ,  H01L23/498 ,  H01L25/065

CPC classification number: H01L24/73 ,  H01L23/3157 ,  H01L23/481 ,  H01L23/49822 ,  H01L24/06 ,  H01L25/0652 ,  H01L2224/06177 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06589

Abstract: A semiconductor package includes a first semiconductor chip that has a mount region and an overhang region, a substrate disposed on a bottom surface at the mount region of the first semiconductor chip, and a molding layer disposed on the substrate. The molding layer includes a first molding pattern disposed on a bottom surface at the overhang region of the first semiconductor chip and covering a sidewall of the substrate, and a second molding pattern on the first molding pattern and covering a sidewall of the first semiconductor chip.

公开(公告)号：US11637070B2

公开(公告)日：2023-04-25

申请号：US17106273

申请日：2020-11-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hae-Jung Yu ,  Kyung Suk Oh

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/683 ,  H01L23/13 ,  H01L23/31 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00

Abstract: A semiconductor package includes a redistribution layer having a first surface and a second surface opposite to each other, the redistribution layer including a plurality of first redistribution pads on the first surface, a semiconductor chip on the second surface of the redistribution layer, an active surface of the semiconductor chip facing the redistribution layer, a plurality of conductive structures on the second surface of the redistribution layer, the plurality of conductive structures being spaced apart from the semiconductor chip, and a plurality of external connection terminals on and coupled to the conductive structures, the plurality of first redistribution pads have a pitch smaller than a pitch of the plurality of external connection terminals.

公开(公告)号：US20140299980A1

公开(公告)日：2014-10-09

申请号：US14160008

申请日：2014-01-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eun-Kyoung Choi ,  Jong-Youn Kim ,  Sang-Wook Park ,  Hae-Jung Yu ,  In-Young Lee ,  Sang-Uk Han ,  Ji-Seok Hong

IPC: H01L23/522 ,  H01L23/34

CPC classification number: H01L24/97 ,  H01L21/561 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/36 ,  H01L23/3737 ,  H01L23/4334 ,  H01L23/481 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06568 ,  H01L2225/06589 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00

Abstract: Semiconductor packages including a heat spreader and methods of forming the same are provided. The semiconductor packages may include a first semiconductor chip, a second semiconductor chip, and a heat spreader stacked sequentially. The semiconductor packages may also include a thermal interface material (TIM) layer surrounding the second semiconductor chip and directly contacting a sidewall of the second semiconductor chip. An upper surface of the TIM layer may directly contact a lower surface of the heat spreader, and a sidewall of the TIM layer may be substantially coplanar with a sidewall of the heat spreader. In some embodiments, a sidewall of the first semiconductor chip may be substantially coplanar with the sidewall of the TIM layer.

Abstract translation: 提供了包括散热器的半导体封装及其形成方法。 半导体封装可以包括顺序堆叠的第一半导体芯片，第二半导体芯片和散热器。 半导体封装还可以包括围绕第二半导体芯片并直接接触第二半导体芯片的侧壁的热界面材料（TIM）层。 TIM层的上表面可以直接接触散热器的下表面，并且TIM层的侧壁可以与散热器的侧壁基本上共面。 在一些实施例中，第一半导体芯片的侧壁可以与TIM层的侧壁基本共面。

公开(公告)号：US12218070B2

公开(公告)日：2025-02-04

申请号：US18133656

申请日：2023-04-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hae-Jung Yu ,  Kyung Suk Oh

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/683 ,  H01L23/00 ,  H01L23/13 ,  H01L23/31 ,  H01L25/00 ,  H01L25/065

Abstract: A semiconductor package includes a redistribution layer having a first surface and a second surface opposite to each other, the redistribution layer including a plurality of first redistribution pads on the first surface, a semiconductor chip on the second surface of the redistribution layer, an active surface of the semiconductor chip facing the redistribution layer, a plurality of conductive structures on the second surface of the redistribution layer, the plurality of conductive structures being spaced apart from the semiconductor chip, and a plurality of external connection terminals on and coupled to the conductive structures, the plurality of first redistribution pads have a pitch smaller than a pitch of the plurality of external connection terminals.

公开(公告)号：US10854551B2

公开(公告)日：2020-12-01

申请号：US16161460

申请日：2018-10-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hae-Jung Yu ,  Kyung Suk Oh

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/683 ,  H01L23/13 ,  H01L23/31 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00

Abstract: A semiconductor package includes a redistribution layer having a first surface and a second surface opposite to each other, the redistribution layer including a plurality of first redistribution pads on the first surface, a semiconductor chip on the second surface of the redistribution layer, an active surface of the semiconductor chip facing the redistribution layer, a plurality of conductive structures on the second surface of the redistribution layer, the plurality of conductive structures being spaced apart from the semiconductor chip, and a plurality of external connection terminals on and coupled to the conductive structures, the plurality of first redistribution pads have a pitch smaller than a pitch of the plurality of external connection terminals.