公开(公告)号：US10396094B2

公开(公告)日：2019-08-27

申请号：US15849121

申请日：2017-12-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ji-Hoon Choi ,  Sunggil Kim ,  Seulye Kim ,  Hongsuk Kim ,  Phil Ouk Nam ,  Jaeyoung Ahn

IPC: H01L21/02 ,  H01L21/28 ,  H01L29/06 ,  H01L29/10 ,  H01L29/51 ,  H01L29/66 ,  H01L21/311 ,  H01L29/792 ,  H01L27/1157 ,  H01L27/11565 ,  H01L27/11582

Abstract: A three-dimensional semiconductor device includes gate electrodes sequentially stacked on a substrate, a channel structure penetrating the gate electrodes and being connected to the substrate, an insulating gap-fill pattern provided within the channel structure and surrounded by the channel structure as viewed in a plan view, and a conductive pattern on the insulating gap-fill pattern. At least a portion of the insulating gap-fill pattern is received in the conductive pattern, and at least a portion of the conductive pattern is interposed between at least that portion of the insulating gap-fill pattern and the channel structure.

公开(公告)号：US10263006B2

公开(公告)日：2019-04-16

申请号：US15480983

申请日：2017-04-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung Gil Kim ,  Ji-Hoon Choi ,  Dongkyum Kim ,  Jintae Noh ,  Seulye Kim ,  Hong Suk Kim ,  Phil Ouk Nam ,  Jaeyoung Ahn

IPC: H01L27/11556 ,  H01L27/11582 ,  H01L29/08 ,  H01L29/10 ,  H01L27/1157 ,  H01L29/423

Abstract: A semiconductor memory device may include: a stacking structure including a plurality of insulating layers and a plurality of gate electrodes alternately stacked on a substrate; a lower semiconductor pattern that protrudes from the top of the substrate; a vertical insulating pattern that extends in a vertical direction from the substrate and penetrates the stacking structure; and a vertical channel pattern on the inner surface of the vertical insulating pattern and contacting the lower semiconductor pattern, wherein an upper part of the lower semiconductor pattern includes a recess region including a curve-shaped profile, and in the recess region, the outer surface of a lower part of the vertical channel pattern contacts the lower semiconductor pattern along a curve of the recess region.

公开(公告)号：US11910607B2

公开(公告)日：2024-02-20

申请号：US17881707

申请日：2022-08-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung-Hwan Kim ,  Sunggil Kim ,  Dongkyum Kim ,  Seulye Kim ,  Ji-Hoon Choi

IPC: H01L21/00 ,  H10B43/27 ,  H01L29/04 ,  H01L29/792 ,  H01L29/423 ,  H10B43/10 ,  H10B43/35 ,  H10B43/40

CPC classification number: H10B43/27 ,  H01L29/04 ,  H01L29/42344 ,  H01L29/7926 ,  H10B43/10 ,  H10B43/35 ,  H10B43/40

Abstract: A three-dimensional semiconductor memory device is disclosed. The device may include a first source conductive pattern comprising a polycrystalline material including first crystal grains on a substrate, the substrate may comprising a polycrystalline material including second crystal grains, a grain size of the first crystal grains being smaller than a grain size of the second crystal grains, a stack including a plurality of gate electrodes, the plurality of gates stacked on the first source conductive pattern, and a vertical channel portion penetrating the stack and the first source conductive pattern, and the vertical channel portion being in contact with a side surface of the first source conductive pattern.

公开(公告)号：US11424264B2

公开(公告)日：2022-08-23

申请号：US16838586

申请日：2020-04-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung-Hwan Kim ,  Sunggil Kim ,  Dongkyum Kim ,  Seulye Kim ,  Ji-Hoon Choi

IPC: H01L21/00 ,  H01L27/11582 ,  H01L29/04 ,  H01L27/11565 ,  H01L29/792 ,  H01L27/11573 ,  H01L29/423 ,  H01L27/1157

Abstract: A three-dimensional semiconductor memory device is disclosed. The device may include a first source conductive pattern comprising a polycrystalline material including first crystal grains on a substrate, the substrate may comprising a polycrystalline material including second crystal grains, a grain size of the first crystal grains being smaller than a grain size of the second crystal grains, a stack including a plurality of gate electrodes, the plurality of gates stacked on the first source conductive pattern, and a vertical channel portion penetrating the stack and the first source conductive pattern, and the vertical channel portion being in contact with a side surface of the first source conductive pattern.

公开(公告)号：US10930739B2

公开(公告)日：2021-02-23

申请号：US16186915

申请日：2018-11-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ji-Hoon Choi ,  Dongkyum Kim ,  Sunggil Kim ,  Seulye Kim ,  Sangsoo Lee ,  Hyeeun Hong

IPC: H01L29/10 ,  H01L27/11556 ,  H01L27/11573 ,  H01L29/423 ,  H01L27/11526 ,  H01L27/11582 ,  H01L27/1157 ,  H01L27/11565 ,  H01L27/11575

Abstract: A three-dimensional semiconductor memory device includes an electrode structure including electrodes vertically stacked on a semiconductor layer, a vertical semiconductor pattern penetrating the electrode structure and connected to the semiconductor layer, and a vertical insulating pattern between the electrode structure and the vertical semiconductor pattern. The vertical insulating pattern includes a sidewall portion on a sidewall of the electrode structure, and a protrusion extending from the sidewall portion along a portion of a top surface of the semiconductor layer. The vertical semiconductor pattern includes a vertical channel portion having a first thickness and extending along the sidewall portion of the vertical insulating pattern, and a contact portion extending from the vertical channel portion and conformally along the protrusion of the vertical insulating pattern and the top surface of the semiconductor layer. The contact portion has a second thickness greater than the first thickness.

公开(公告)号：US20190206886A1

公开(公告)日：2019-07-04

申请号：US16298247

申请日：2019-03-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung Gil Kim ,  Ji-Hoon Choi ,  Dongkyum Kim ,  Jintae Noh ,  Seulye Kim ,  Hong Suk Kim ,  Phil Ouk Nam ,  Jaeyoung Ahn

IPC: H01L27/11556 ,  H01L29/10 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/08

CPC classification number: H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/42324 ,  H01L29/4234 ,  H01L29/42364

Abstract: A semiconductor memory device may include: a stacking structure including a plurality of insulating layers and a plurality of gate electrodes alternately stacked on a substrate; a lower semiconductor pattern that protrudes from the top of the substrate; a vertical insulating pattern that extends in a vertical direction from the substrate and penetrates the stacking structure; and a vertical channel pattern on the inner surface of the vertical insulating pattern and contacting the lower semiconductor pattern, wherein an upper part of the lower semiconductor pattern includes a recess region including a curve-shaped profile, and in the recess region, the outer surface of a lower part of the vertical channel pattern contacts the lower semiconductor pattern along a curve of the recess region.

公开(公告)号：US11521987B2

公开(公告)日：2022-12-06

申请号：US17195756

申请日：2021-03-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ji-Hoon Choi ,  Sung-Gil Kim ,  Jung-Hwan Kim ,  Chan-Hyoung Kim ,  Woo-Sung Lee

IPC: H01L27/00 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/11556 ,  H01L27/11524

Abstract: A vertical memory device may include a channel connecting pattern on a substrate, gate electrodes spaced apart from each other in a first direction on the channel connecting pattern, and a channel extending in the first direction through the gate electrodes and the channel connecting pattern. Each of the electrodes may extend in a second direction substantially parallel to an upper surface of the substrate, and the first direction may be substantially perpendicular to the upper surface of the substrate. An end portion of the channel connecting pattern in a third direction substantially parallel to the upper surface of the substrate and substantially perpendicular to the second direction may have an upper surface higher than an upper surface of other portions of the channel connecting pattern except for a portion thereof adjacent the channel.

公开(公告)号：US11282856B2

公开(公告)日：2022-03-22

申请号：US16845615

申请日：2020-04-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ji-Hoon Choi ,  Sunggil Kim ,  Seulye Kim ,  HongSuk Kim ,  Phil Ouk Nam ,  Jaeyoung Ahn

IPC: H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L21/02 ,  H01L21/306 ,  H01L21/3065 ,  H01L27/11573 ,  H01L27/11575 ,  H01L29/792 ,  H01L29/423 ,  H01L29/04 ,  H01L27/11565 ,  H01L29/51

Abstract: A semiconductor device may include a substrate, an electrode structure including electrodes stacked on the substrate, an upper semiconductor pattern penetrating at least a portion of the electrode structure, and a lower semiconductor pattern between the substrate and the upper semiconductor pattern. The upper semiconductor pattern includes a gap-filling portion and a sidewall portion extending from the gap-filling portion in a direction away from the substrate, the lower semiconductor pattern includes a concave top surface, the gap-filling portion fills a region enclosed by the concave top surface, a top surface of the gap-filling portion has a rounded shape that is deformed toward the substrate, and a thickness of the sidewall portion is less than a thickness of the gap-filling portion.

公开(公告)号：US20200176467A1

公开(公告)日：2020-06-04

申请号：US16516756

申请日：2019-07-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ji-Hoon Choi ,  Sung-Gil Kim ,  Jung-Hwan Kim ,  Chan-Hyoung Kim ,  Woo-Sung Lee

IPC: H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157

Abstract: A vertical memory device may include a channel connecting pattern on a substrate, gate electrodes spaced apart from each other in a first direction on the channel connecting pattern, and a channel extending in the first direction through the gate electrodes and the channel connecting pattern. Each of the electrodes may extend in a second direction substantially parallel to an upper surface of the substrate, and the first direction may be substantially perpendicular to the upper surface of the substrate. An end portion of the channel connecting pattern in a third direction substantially parallel to the upper surface of the substrate and substantially perpendicular to the second direction may have an upper surface higher than an upper surface of other portions of the channel connecting pattern except for a portion thereof adjacent the channel.

公开(公告)号：US20170022610A1

公开(公告)日：2017-01-26

申请号：US15066318

申请日：2016-03-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eun-Sung Seo ,  Yong-Kwon Kim ,  Young-Jin Noh ,  Young-Chang Song ,  Jae-Myung Choe ,  Ji-Hoon Choi ,  Sang-Cheol HA

IPC: C23C16/455 ,  C23C16/44 ,  C23C16/24

CPC classification number: C23C16/4412 ,  C23C16/045 ,  C23C16/45502 ,  C23C16/45546 ,  C23C16/45578 ,  C23C16/4584 ,  H01L28/00

Abstract: A wafer processing apparatus may include a reaction tube extending in a vertical direction and defining a process chamber for receiving a boat that holds a plurality of wafers. A gas injector may be configured to supply a reaction gas into the process chamber and may include a gas distributor extending in the vertical direction in the reaction tube. The gas injector may have a plurality of ejection holes for spraying the reaction gas. An inner diameter of the gas distributor may be at least 10 mm, and a sectional area ratio of the total sectional area of the ejection holes to a sectional area of the gas distributor is about 0.3 or less.

Abstract translation: 晶片处理装置可以包括在垂直方向上延伸的反应管并且限定用于接纳保持多个晶片的船的处理室。 气体注射器可以被配置为将反应气体供应到处理室中，并且可以包括在反应管中沿垂直方向延伸的气体分布器。 气体喷射器可以具有用于喷射反应气体的多个喷射孔。 气体分配器的内径可以为至少10mm，并且喷射孔的总截面积与气体分配器的截面面积的截面积比为约0.3以下。