公开(公告)号：US20170345713A1

公开(公告)日：2017-11-30

申请号：US15638551

申请日：2017-06-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jin-ho Chun ,  Byung-lyul PARK ,  Hyun-soo CHUNG ,  Gil-heyun CHOI ,  Son-kwan HWANG

IPC: H01L21/768 ,  H01L23/00 ,  H01L25/065 ,  H01L23/48 ,  H01L23/544 ,  H01L23/31

CPC classification number: H01L21/76898 ,  H01L21/768 ,  H01L21/76841 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/544 ,  H01L24/03 ,  H01L24/81 ,  H01L25/065 ,  H01L25/0657 ,  H01L2223/54426 ,  H01L2224/03462 ,  H01L2224/0401 ,  H01L2224/05 ,  H01L2224/05025 ,  H01L2224/05552 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/13 ,  H01L2224/13023 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/8185 ,  H01L2924/00014 ,  H01L2924/06 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/00

Abstract: A semiconductor chip including through silicon vias (TSVs), wherein the TSVs may be prevented from bending and the method of fabricating the semiconductor chip may be simplified, and a method of fabricating the semiconductor chip. The semiconductor chip includes a silicon substrate having a first surface and a second surface; a plurality of TSVs which penetrate the silicon substrate and protrude above the second surface of the silicon substrate; a polymer pattern layer which is formed on the second surface of the silicon substrate, surrounds side surfaces of the protruding portion of each of the TSVs, and comprises a flat first portion and a second portion protruding above the first portion; and a plated pad which is formed on the polymer pattern layer and covers a portion of each of the TSVs exposed from the polymer pattern layer.

公开(公告)号：US08957526B2

公开(公告)日：2015-02-17

申请号：US13733923

申请日：2013-01-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jin-ho Chun ,  Byung-lyul Park ,  Hyun-soo Chung ,  Gil-heyun Choi ,  Son-kwan Hwang

IPC: H01L23/52 ,  H01L29/24 ,  H01L23/48 ,  H01L21/768 ,  H01L25/065 ,  H01L23/31

CPC classification number: H01L21/76898 ,  H01L21/768 ,  H01L21/76841 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/544 ,  H01L24/03 ,  H01L24/81 ,  H01L25/065 ,  H01L25/0657 ,  H01L2223/54426 ,  H01L2224/03462 ,  H01L2224/0401 ,  H01L2224/05 ,  H01L2224/05025 ,  H01L2224/05552 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/13 ,  H01L2224/13023 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/8185 ,  H01L2924/00014 ,  H01L2924/06 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/00

Abstract: A semiconductor chip including through silicon vias (TSVs), wherein the TSVs may be prevented from bending and the method of fabricating the semiconductor chip may be simplified, and a method of fabricating the semiconductor chip. The semiconductor chip includes a silicon substrate having a first surface and a second surface; a plurality of TSVs which penetrate the silicon substrate and protrude above the second surface of the silicon substrate; a polymer pattern layer which is formed on the second surface of the silicon substrate, surrounds side surfaces of the protruding portion of each of the TSVs, and comprises a flat first portion and a second portion protruding above the first portion; and a plated pad which is formed on the polymer pattern layer and covers a portion of each of the TSVs exposed from the polymer pattern layer.

Abstract translation: 包括通过硅通孔（TSV）的半导体芯片，其中可以防止TSV弯曲，并且可以简化制造半导体芯片的方法，以及制造半导体芯片的方法。 半导体芯片包括具有第一表面和第二表面的硅衬底; 多个TSV，其穿透硅衬底并突出在硅衬底的第二表面上方; 形成在硅衬底的第二表面上的聚合物图案层围绕每个TSV的突出部分的侧表面，并且包括平坦的第一部分和在第一部分上方突出的第二部分; 以及形成在聚合物图案层上并覆盖从聚合物图案层露出的每个TSV的一部分的电镀垫。

公开(公告)号：US11251144B2

公开(公告)日：2022-02-15

申请号：US16668146

申请日：2019-10-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jeong-gi Jin ,  Nae-in Lee ,  Jum-yong Park ,  Jin-ho Chun ,  Seong-min Son ,  Ho-jin Lee

IPC: H01L23/00 ,  H01L23/31 ,  H01L25/10 ,  H01L25/065

Abstract: A semiconductor chip includes a semiconductor substrate including a bump region and a non-bump region, a bump on the bump region, and a passivation layer on the bump region and the non-bump region of the semiconductor substrate. No bump is on the non-bump region. A thickness of the passivation layer in the bump region is thicker than a thickness of the passivation layer in the non-bump region. The passivation layer includes a step between the bump region and the non-bump region.

公开(公告)号：US10483224B2

公开(公告)日：2019-11-19

申请号：US15791709

申请日：2017-10-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jeong-gi Jin ,  Nae-in Lee ,  Jum-yong Park ,  Jin-ho Chun ,  Seong-min Son ,  Ho-jin Lee

IPC: H01L23/00 ,  H01L23/31 ,  H01L25/065 ,  H01L25/10

Abstract: A semiconductor chip includes a semiconductor substrate including a bump region and a non-bump region, a bump on the bump region, and a passivation layer on the bump region and the non-bump region of the semiconductor substrate. No bump is on the non-bump region. A thickness of the passivation layer in the bump region is thicker than a thickness of the passivation layer in the non-bump region. The passivation layer includes a step between the bump region and the non-bump region.

公开(公告)号：US20180138137A1

公开(公告)日：2018-05-17

申请号：US15791709

申请日：2017-10-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jeong-gi JIN ,  Nae-in Lee ,  Jum-yong Park ,  Jin-ho Chun ,  Seong-min Son ,  Ho-jin Lee

IPC: H01L23/00 ,  H01L25/065

CPC classification number: H01L24/05 ,  H01L23/3157 ,  H01L24/02 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/02126 ,  H01L2224/02206 ,  H01L2224/0221 ,  H01L2224/02215 ,  H01L2224/02335 ,  H01L2224/0401 ,  H01L2224/05025 ,  H01L2224/05564 ,  H01L2224/11849 ,  H01L2224/13013 ,  H01L2224/13025 ,  H01L2224/13026 ,  H01L2224/13101 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/1403 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81815 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06565 ,  H01L2225/06572 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/10253 ,  H01L2924/1432 ,  H01L2924/1434 ,  H01L2924/1438 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A semiconductor chip includes a semiconductor substrate including a bump region and a non-bump region, a bump on the bump region, and a passivation layer on the bump region and the non-bump region of the semiconductor substrate. No bump is on the non-bump region. A thickness of the passivation layer in the bump region is thicker than a thickness of the passivation layer in the non-bump region. The passivation layer includes a step between the bump region and the non-bump region.

公开(公告)号：US20200066666A1

公开(公告)日：2020-02-27

申请号：US16668146

申请日：2019-10-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jeong-gi Jin ,  Nae-in Lee ,  Jum-yong Park ,  Jin-ho Chun ,  Seong-min Son ,  Ho-jin Lee

IPC: H01L23/00 ,  H01L23/31

Abstract: A semiconductor chip includes a semiconductor substrate including a bump region and a non-bump region, a bump on the bump region, and a passivation layer on the bump region and the non-bump region of the semiconductor substrate. No bump is on the non-bump region. A thickness of the passivation layer in the bump region is thicker than a thickness of the passivation layer in the non-bump region. The passivation layer includes a step between the bump region and the non-bump region.

公开(公告)号：US09461007B2

公开(公告)日：2016-10-04

申请号：US14796506

申请日：2015-07-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jin-ho Chun ,  Pil-kyu Kang ,  Byung-lyul Park ,  Jae-hwa Park ,  Ju-il Choi

IPC: H01L23/528 ,  H01L23/00 ,  H01L23/532 ,  H01L23/31 ,  H01L25/00

CPC classification number: H01L24/08 ,  H01L23/3192 ,  H01L23/5283 ,  H01L23/53238 ,  H01L23/53295 ,  H01L24/05 ,  H01L24/80 ,  H01L24/94 ,  H01L25/50 ,  H01L2224/05025 ,  H01L2224/05147 ,  H01L2224/05546 ,  H01L2224/05547 ,  H01L2224/05647 ,  H01L2224/0569 ,  H01L2224/08145 ,  H01L2224/80862 ,  H01L2224/80895 ,  H01L2224/80905 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06548 ,  H01L2924/06 ,  H01L2924/0695 ,  H01L2924/07025 ,  H01L2224/80 ,  H01L2924/00014

Abstract: A wafer-to-wafer bonding structure may include: a first wafer including a first insulating layer on a first substrate and on a first copper (Cu) pad that penetrates the first insulating layer and has portions protruding from an upper surface of the first insulating layer, and a first barrier metal layer on a lower surface and sides of the first Cu pad; a second wafer including a second insulating layer on a second substrate and on a second copper (Cu) pad that penetrates the second insulating layer, has portions protruding from an upper surface of the second insulating layer, and is bonded to the first Cu pad, and a second barrier metal layer on a lower surface and sides of the second Cu pad; and a polymer layer covering protruding sides of the first and second barrier metal layers and disposed between the first and second wafers.

Abstract translation: 晶片到晶片接合结构可以包括：第一晶片，其包括在第一基板上的第一绝缘层和穿过第一绝缘层的第一铜（Cu）焊盘，并且具有从第一绝缘层的上表面突出的部分 层和第一Cu衬垫的下表面和侧面上的第一阻挡金属层; 包括在第二基板上的第二绝缘层和穿过第二绝缘层的第二铜（Cu）焊盘上的第二晶片具有从第二绝缘层的上表面突出的部分并且接合到第一Cu焊盘， 以及在所述第二Cu垫的下表面和侧面上的第二阻挡金属层; 以及覆盖第一和第二阻挡金属层的突出侧并设置在第一和第二晶片之间的聚合物层。

公开(公告)号：US20130264720A1

公开(公告)日：2013-10-10

申请号：US13733923

申请日：2013-01-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jin-ho Chun ,  Byung-lyul Park ,  Hyun-soo Chung ,  Gil-heyun Choi ,  Son-kwan Hwang

IPC: H01L23/48 ,  H01L21/768

CPC classification number: H01L21/76898 ,  H01L21/768 ,  H01L21/76841 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/544 ,  H01L24/03 ,  H01L24/81 ,  H01L25/065 ,  H01L25/0657 ,  H01L2223/54426 ,  H01L2224/03462 ,  H01L2224/0401 ,  H01L2224/05 ,  H01L2224/05025 ,  H01L2224/05552 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/13 ,  H01L2224/13023 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/8185 ,  H01L2924/00014 ,  H01L2924/06 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/00

Abstract: A semiconductor chip including through silicon vias (TSVs), wherein the TSVs may be prevented from bending and the method of fabricating the semiconductor chip may be simplified, and a method of fabricating the semiconductor chip. The semiconductor chip includes a silicon substrate having a first surface and a second surface; a plurality of TSVs which penetrate the silicon substrate and protrude above the second surface of the silicon substrate; a polymer pattern layer which is formed on the second surface of the silicon substrate, surrounds side surfaces of the protruding portion of each of the TSVs, and comprises a flat first portion and a second portion protruding above the first portion; and a plated pad which is formed on the polymer pattern layer and covers a portion of each of the TSVs exposed from the polymer pattern layer.

Abstract translation: 包括通过硅通孔（TSV）的半导体芯片，其中可以防止TSV弯曲，并且可以简化制造半导体芯片的方法，以及制造半导体芯片的方法。 半导体芯片包括具有第一表面和第二表面的硅衬底; 多个TSV，其穿透硅衬底并突出在硅衬底的第二表面上方; 形成在硅衬底的第二表面上的聚合物图案层围绕每个TSV的突出部分的侧表面，并且包括平坦的第一部分和在第一部分上方突出的第二部分; 以及形成在聚合物图案层上并覆盖从聚合物图案层露出的每个TSV的一部分的电镀垫。

公开(公告)号：US11798906B2

公开(公告)日：2023-10-24

申请号：US17551548

申请日：2021-12-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jeong-gi Jin ,  Nae-in Lee ,  Jum-yong Park ,  Jin-ho Chun ,  Seong-min Son ,  Ho-Jin Lee

IPC: H01L23/00 ,  H01L23/31 ,  H01L25/10 ,  H01L25/065

CPC classification number: H01L24/05 ,  H01L23/3157 ,  H01L24/02 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/0221 ,  H01L2224/02126 ,  H01L2224/02206 ,  H01L2224/02215 ,  H01L2224/02335 ,  H01L2224/0401 ,  H01L2224/05025 ,  H01L2224/05564 ,  H01L2224/11849 ,  H01L2224/13013 ,  H01L2224/13025 ,  H01L2224/13026 ,  H01L2224/13101 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/1403 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81815 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06565 ,  H01L2225/06572 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/10253 ,  H01L2924/1432 ,  H01L2924/1434 ,  H01L2924/1438 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2224/13101 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2224/13144 ,  H01L2924/00014 ,  H01L2224/13147 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/73204 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2924/00

Abstract: A semiconductor chip includes a semiconductor substrate including a bump region and a non-bump region, a bump on the bump region, and a passivation layer on the bump region and the non-bump region of the semiconductor substrate. No bump is on the non-bump region. A thickness of the passivation layer in the bump region is thicker than a thickness of the passivation layer in the non-bump region. The passivation layer includes a step between the bump region and the non-bump region.

公开(公告)号：US09698051B2

公开(公告)日：2017-07-04

申请号：US14590036

申请日：2015-01-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jin-ho Chun ,  Byung-Iyul Park ,  Hyun-soo Chung ,  Gil-heyun Choi ,  Son-kwan Hwang

IPC: H01L23/52 ,  H01L23/48 ,  H01L29/24 ,  H01L21/768 ,  H01L25/065 ,  H01L23/544 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L21/76898 ,  H01L21/768 ,  H01L21/76841 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/544 ,  H01L24/03 ,  H01L24/81 ,  H01L25/065 ,  H01L25/0657 ,  H01L2223/54426 ,  H01L2224/03462 ,  H01L2224/0401 ,  H01L2224/05 ,  H01L2224/05025 ,  H01L2224/05552 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/13 ,  H01L2224/13023 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/8185 ,  H01L2924/00014 ,  H01L2924/06 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/00

Abstract: A semiconductor chip including through silicon vias (TSVs), wherein the TSVs may be prevented from bending and the method of fabricating the semiconductor chip may be simplified, and a method of fabricating the semiconductor chip. The semiconductor chip includes a silicon substrate having a first surface and a second surface; a plurality of TSVs which penetrate the silicon substrate and protrude above the second surface of the silicon substrate; a polymer pattern layer which is formed on the second surface of the silicon substrate, surrounds side surfaces of the protruding portion of each of the TSVs, and comprises a flat first portion and a second portion protruding above the first portion; and a plated pad which is formed on the polymer pattern layer and covers a portion of each of the TSVs exposed from the polymer pattern layer.