公开(公告)号：US20150111346A1

公开(公告)日：2015-04-23

申请号：US14590036

申请日：2015-01-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jin-ho Chun ,  Byung-Iyul PARK ,  Hyun-soo CHUNG ,  Gil-heyun CHOI ,  Son-kwan HWANG

IPC: H01L21/768 ,  H01L23/544 ,  H01L23/00

CPC classification number: H01L21/76898 ,  H01L21/768 ,  H01L21/76841 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/544 ,  H01L24/03 ,  H01L24/81 ,  H01L25/065 ,  H01L25/0657 ,  H01L2223/54426 ,  H01L2224/03462 ,  H01L2224/0401 ,  H01L2224/05 ,  H01L2224/05025 ,  H01L2224/05552 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/13 ,  H01L2224/13023 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/8185 ,  H01L2924/00014 ,  H01L2924/06 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/00

Abstract: A semiconductor chip including through silicon vias (TSVs), wherein the TSVs may be prevented from bending and the method of fabricating the semiconductor chip may be simplified, and a method of fabricating the semiconductor chip. The semiconductor chip includes a silicon substrate having a first surface and a second surface; a plurality of TSVs which penetrate the silicon substrate and protrude above the second surface of the silicon substrate; a polymer pattern layer which is formed on the second surface of the silicon substrate, surrounds side surfaces of the protruding portion of each of the TSVs, and comprises a flat first portion and a second portion protruding above the first portion; and a plated pad which is formed on the polymer pattern layer and covers a portion of each of the TSVs exposed from the polymer pattern layer.

Abstract translation: 包括通过硅通孔（TSV）的半导体芯片，其中可以防止TSV弯曲，并且可以简化制造半导体芯片的方法，以及制造半导体芯片的方法。 半导体芯片包括具有第一表面和第二表面的硅衬底; 多个TSV，其穿透硅衬底并突出在硅衬底的第二表面上方; 形成在硅衬底的第二表面上的聚合物图案层围绕每个TSV的突出部分的侧表面，并且包括平坦的第一部分和在第一部分上方突出的第二部分; 以及形成在聚合物图案层上并覆盖从聚合物图案层露出的每个TSV的一部分的电镀垫。

公开(公告)号：US20190051612A1

公开(公告)日：2019-02-14

申请号：US15869517

申请日：2018-01-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young-Iyong KIM ,  Hyun-soo CHUNG ,  Dong-hyeon JANG

IPC: H01L23/552 ,  H01L23/00 ,  H01L23/34 ,  H01L23/538

CPC classification number: H01L23/552 ,  H01L23/345 ,  H01L23/367 ,  H01L23/4334 ,  H01L23/5384 ,  H01L24/10 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/19 ,  H01L24/20 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L24/92 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/12105 ,  H01L2224/13025 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/29339 ,  H01L2224/29344 ,  H01L2224/29347 ,  H01L2224/29355 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73267 ,  H01L2224/83851 ,  H01L2224/83862 ,  H01L2224/83874 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/3025 ,  H01L2924/3511 ,  H01L2224/83 ,  H01L2924/0665 ,  H01L2924/069 ,  H01L2924/0635

Abstract: A semiconductor package including a heat spreading layer having at least one hole, a first semiconductor chip below the heat spreading layer, a redistribution structure below the first semiconductor chip, a first mold layer between the heat spreading layer and the redistribution structure, a shielding wall extending from the redistribution structure and the heat spreading layer and surrounding the first semiconductor chip, and a first conductive pillar extending from the redistribution structure into the hole may be provided.

公开(公告)号：US20170345713A1

公开(公告)日：2017-11-30

申请号：US15638551

申请日：2017-06-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jin-ho Chun ,  Byung-lyul PARK ,  Hyun-soo CHUNG ,  Gil-heyun CHOI ,  Son-kwan HWANG

IPC: H01L21/768 ,  H01L23/00 ,  H01L25/065 ,  H01L23/48 ,  H01L23/544 ,  H01L23/31

CPC classification number: H01L21/76898 ,  H01L21/768 ,  H01L21/76841 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/544 ,  H01L24/03 ,  H01L24/81 ,  H01L25/065 ,  H01L25/0657 ,  H01L2223/54426 ,  H01L2224/03462 ,  H01L2224/0401 ,  H01L2224/05 ,  H01L2224/05025 ,  H01L2224/05552 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/13 ,  H01L2224/13023 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/8185 ,  H01L2924/00014 ,  H01L2924/06 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/00

Abstract: A semiconductor chip including through silicon vias (TSVs), wherein the TSVs may be prevented from bending and the method of fabricating the semiconductor chip may be simplified, and a method of fabricating the semiconductor chip. The semiconductor chip includes a silicon substrate having a first surface and a second surface; a plurality of TSVs which penetrate the silicon substrate and protrude above the second surface of the silicon substrate; a polymer pattern layer which is formed on the second surface of the silicon substrate, surrounds side surfaces of the protruding portion of each of the TSVs, and comprises a flat first portion and a second portion protruding above the first portion; and a plated pad which is formed on the polymer pattern layer and covers a portion of each of the TSVs exposed from the polymer pattern layer.

公开(公告)号：US20170011976A1

公开(公告)日：2017-01-12

申请号：US15175017

申请日：2016-06-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Myeong-soon PARK ,  Hyun-soo CHUNG ,  Chan-ho LEE

IPC: H01L21/66 ,  H01L27/108

Abstract: A semiconductor chip is disclosed that includes a chip pad disposed in a first region of a chip body, a redistribution wiring test pad disposed in the first region of the chip body spaced apart from the chip pad and connected to the chip pad through a redistribution wiring structure, and a redistribution wiring connection pad disposed in the first region of the chip body or a second region of the chip body and connected to the chip pad through the redistribution wiring structure.

Abstract translation: 公开了一种半导体芯片，其包括设置在芯片体的第一区域中的芯片焊盘，布置在芯片体的与芯片焊盘间隔开的第一区域中的再分配布线测试焊盘，并通过再分配布线连接到芯片焊盘 结构，以及设置在芯片体的第一区域或芯片体的第二区域中并且通过再分配布线结构连接到芯片焊盘的再分配布线连接焊盘。

公开(公告)号：US20150364432A1

公开(公告)日：2015-12-17

申请号：US14702662

申请日：2015-05-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyun-soo CHUNG ,  Tae-je CHO ,  Jung-seok AHN ,  In-young LEE

IPC: H01L23/00 ,  H01L23/29 ,  H01L23/48 ,  H01L21/78 ,  H01L21/304 ,  H01L23/31 ,  H01L25/00 ,  H01L21/56 ,  H01L25/065 ,  H01L21/768 ,  H01L21/48 ,  H01L23/495 ,  H01L21/683

CPC classification number: H01L23/562 ,  H01L21/304 ,  H01L21/4803 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/76898 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/481 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68381 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/97 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012

Abstract: Embodiments of the inventive aspect include a method of manufacturing a semiconductor package including a plurality of stacked semiconductor chips in which edges of a semiconductor wafer substrate may be prevented from being damaged or cracked when the semiconductor package is manufactured at a wafer level, while a diameter of a molding element is greater than a diameter of the semiconductor wafer substrate. The molding element may cover a surface of the wafer substrate and the plurality of stacked semiconductor chips. Embodiments may include a wafer level semiconductor package including a circular substrate having a first diameter, a circular passivation layer attached to the circular substrate, the passivation layer having the first diameter, and a circular molding element covering surfaces of the plurality of semiconductor chips, and covering an active area of the substrate. The circular molding element may have a second diameter that is greater than the first diameter.

Abstract translation: 本发明的实施例包括一种制造半导体封装的方法，该半导体封装包括多个层叠半导体芯片，其中半导体封装在晶片级制造时可以防止半导体晶片衬底的边缘损坏或破裂，而直径 的模制元件大于半导体晶片衬底的直径。 成型元件可以覆盖晶片基板的表面和多个堆叠的半导体芯片。 实施例可以包括晶片级半导体封装，其包括具有第一直径的圆形衬底，附着到圆形衬底的圆形钝化层，具有第一直径的钝化层和覆盖多个半导体芯片的表面的圆形模制元件，以及 覆盖基板的有效区域。 圆形模制元件可以具有大于第一直径的第二直径。