公开(公告)号：US11411024B2

公开(公告)日：2022-08-09

申请号：US16995084

申请日：2020-08-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung-Yun Lee ,  Jae-Hoon Jang ,  Jae-Duk Lee ,  Joon-Hee Lee ,  Young-Jin Jung

IPC: H01L27/11556 ,  H01L27/11582 ,  H01L21/768 ,  H01L21/308 ,  H01L21/28 ,  H01L27/11565

Abstract: A vertical type semiconductor device includes insulation patterns on a substrate and spaced apart from each other in a first direction perpendicular to a top surface of the substrate, a channel structure on the substrate and penetrating through the insulation patterns, a first conductive pattern partially filling a gap between the insulation patterns adjacent to each other in the first direction and the channel structure and having a slit in a surface thereof, the slit extending in a direction parallel with the top surface of the substrate, and a second conductive pattern on the first conductive pattern in the gap and filling the slit.

公开(公告)号：US10204918B2

公开(公告)日：2019-02-12

申请号：US15285709

申请日：2016-10-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung-Hun Lee ,  Jong-Ho Park ,  Joon-Hee Lee ,  Hee-Jueng Lee

IPC: H01L27/148 ,  H01L27/11573 ,  H01L27/11582 ,  H01L29/04 ,  H01L27/11565 ,  H01L27/11575

Abstract: A memory device includes a memory cell on a first region of a substrate. An active region is in a second region neighboring the first region of the substrate, and an extension direction of the active region has an acute angle with the direction of the substrate. A transistor serving as a peripheral circuit is on the second region of the substrate. In the memory device, defects or failures due to a crystal defects or a dislocation of the substrate may decrease.

公开(公告)号：US09467121B2

公开(公告)日：2016-10-11

申请号：US14468939

申请日：2014-08-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joon-Hee Lee ,  Jong-Won Choi ,  Sang-Wook Han ,  Sung-Jun Lee ,  Young-Taek Lee ,  Young-Gun Pu

IPC: H03B1/00 ,  H03K3/012 ,  H03K17/687 ,  H03K17/14 ,  H03B5/12 ,  H03B5/04

CPC classification number: H03K3/012 ,  H03B5/04 ,  H03B5/1212 ,  H03B5/1228 ,  H03B5/1234 ,  H03B5/124 ,  H03K17/145 ,  H03K17/6877

Abstract: An electronic device for compensating for process variation is provided. The electronic device includes a first circuit configured to consume a current supplied to the first circuit, and a second circuit configured to control the current supplied to the first circuit, The second circuit is configured to generate a signal for controlling the current supplied to the circuit based on a frequency of a pulse signal generated using a second component that is of a same kind as a first component of the first circuit.

Abstract translation: 提供了用于补偿工艺变化的电子设备。 电子设备包括被配置为消耗供应到第一电路的电流的第一电路和被配置为控制提供给第一电路的电流的第二电路。第二电路被配置为产生用于控制提供给电路的电流的信号 基于使用与第一电路的第一分量相同种类的第二分量产生的脉冲信号的频率。

公开(公告)号：US10236298B2

公开(公告)日：2019-03-19

申请号：US15997725

申请日：2018-06-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyun-Suk Kim ,  Joon-Hee Lee ,  Kee-Jeong Rho

IPC: H01L27/11573 ,  H01L49/02 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/11521 ,  H01L27/11568

Abstract: Provided is a vertical non-volatile memory device in which a capacitor constituting a peripheral circuit region is formed as a vertical type so that an area occupied by the capacitor in the entire device can be reduced as compared with a planar capacitor. Thus, a non-volatile memory device may be highly integrated and have a high capacity. The device includes a substrate having a cell region and a peripheral circuit region, a memory cell string including a plurality of vertical memory cells formed in the cell region and channel holes formed to penetrate the vertical memory cells in a first direction vertical to the substrate, an insulating layer formed in the peripheral circuit region on the substrates at substantially the same level as an upper surface of the memory cell string, and a plurality of capacitor electrodes formed on the peripheral circuit region to penetrate at least a portion of the insulating layer in the first direction, the plurality of capacitor electrodes extending parallel to the channel holes. The plurality of capacitor electrodes are spaced apart from one another in a second direction parallel to the substrate, and the insulating layer is interposed between a pair of adjacent capacitor electrodes from among the plurality of capacitor electrodes.

公开(公告)号：US10887845B2

公开(公告)日：2021-01-05

申请号：US16502937

申请日：2019-07-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jae-Hyuk Jang ,  Jung-Woo Kim ,  Chul-Ho Kim ,  Joon-Hee Lee ,  Sang-Wook Han

IPC: H03B27/00 ,  H04W52/24 ,  H04B1/40

Abstract: In an operating method of a radio frequency integrated circuit (RFIC) including a transmission circuit and a reception circuit, the operating method includes receiving, from a modem, first information for setting transmission power of the transmission circuit or second information about a blocker which is a frequency signal unused by the RFIC, obtaining an allowable value of phase noise of a local oscillator included in the transmission circuit, using the first information, obtaining an allowable value of phase noise of a local oscillator included in the reception circuit, using the second information, determining a level of a driving voltage, using the obtained allowable values of the phase noises, and providing the driving voltage to the local oscillators.

公开(公告)号：US09985041B2

公开(公告)日：2018-05-29

申请号：US15295034

申请日：2016-10-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seok-Jung Yun ,  Joon-Hee Lee ,  Seong-Soon Cho

IPC: H01L29/76 ,  H01L29/94 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11597 ,  H01L27/11578 ,  H01L27/1157 ,  H01L29/792 ,  H01L29/788 ,  H01L27/105 ,  H01L29/78 ,  H01L27/11582 ,  H01L49/02

CPC classification number: H01L27/11551 ,  H01L27/1052 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11578 ,  H01L27/11582 ,  H01L27/11597 ,  H01L28/00 ,  H01L29/7827 ,  H01L29/7889 ,  H01L29/7926

Abstract: A vertical memory device may include a plurality of word lines spaced apart in a first direction, each extending in a second direction perpendicular to the first direction and having a first width in a third direction perpendicular to the first and second directions, a dummy word line over an uppermost word line, including an opening and having a portion thereof with the first width in the third direction, a first string selection line (SSL) and a second string selection line (SSL) over the dummy word line, the first and second SSLs being at substantially the same level along the first direction, each of the first and second SSLs having a second width less than the first width in the third direction, and a plurality of vertical channel structures, each through the word lines, the dummy word line, and one of the first and second SSLs.

公开(公告)号：US09318419B2

公开(公告)日：2016-04-19

申请号：US14532484

申请日：2014-11-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sok-Won Lee ,  Joon-Hee Lee ,  Jung-Dal Choi ,  Seong-Min Jo

IPC: H01L29/80 ,  H01L31/112 ,  H01L23/482 ,  H01L23/52 ,  H01L21/768 ,  H01L21/033 ,  H01L21/3213 ,  H01L21/764 ,  H01L27/115 ,  H01L23/522 ,  H01L23/532 ,  H01L23/528

CPC classification number: H01L23/4821 ,  H01L21/0337 ,  H01L21/32139 ,  H01L21/764 ,  H01L21/768 ,  H01L21/7682 ,  H01L21/76837 ,  H01L21/76838 ,  H01L21/76885 ,  H01L21/76895 ,  H01L23/4827 ,  H01L23/52 ,  H01L23/5222 ,  H01L23/528 ,  H01L23/53295 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11565 ,  H01L27/1157 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Conductive line structures, and methods of forming the same, include first and second pattern structures, insulation layer patterns and an insulating interlayer. The first pattern structure includes a conductive line pattern and a hard mask stacked, and extends in a first direction. The second pattern structure includes a second conductive line pattern and another hard mask stacked, and at least a portion of the pattern structure extends in the first direction. The insulation layer patterns contact end portions of the pattern structures. The first pattern structure and an insulation layer pattern form a closed curve shape in plan view, and the second pattern structure and another insulation layer pattern form another closed curve shape in plan view. The insulating interlayer covers upper portions of the pattern structures and the insulation layer patterns, an air gap between the pattern structures, and another air gap between the insulation layer patterns.

Abstract translation: 导电线结构及其形成方法包括第一和第二图案结构，绝缘层图案和绝缘夹层。 第一图案结构包括导线图案和硬掩模，并且沿第一方向延伸。 第二图案结构包括第二导电线图案和另一个硬掩模，并且图案结构的至少一部分沿第一方向延伸。 绝缘层图案接触图形结构的端部。 第一图案结构和绝缘层图案在平面图中形成闭合曲线形状，并且第二图案结构和另一绝缘层图案在平面图中形成另一封闭曲线形状。 绝缘中间层覆盖图案结构的上部和绝缘层图案，图案结构之间的空气间隙和绝缘层图案之间的另一气隙。

公开(公告)号：US10692879B2

公开(公告)日：2020-06-23

申请号：US16260388

申请日：2019-01-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung-Hun Lee ,  Jong-Ho Park ,  Joon-Hee Lee ,  Hee-Jueng Lee

IPC: H01L27/148 ,  H01L27/11573 ,  H01L27/11582 ,  H01L29/04 ,  H01L27/11565 ,  H01L27/11575

Abstract: A memory device includes a memory cell on a first region of a substrate. An active region is in a second region neighboring the first region of the substrate, and an extension direction of the active region has an acute angle with the direction of the substrate. A transistor serving as a peripheral circuit is on the second region of the substrate. In the memory device, defects or failures due to a crystal defects or a dislocation of the substrate may decrease.

公开(公告)号：US10236211B2

公开(公告)日：2019-03-19

申请号：US15956851

申请日：2018-04-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seok-Jung Yun ,  Joon-Hee Lee ,  Seong-Soon Cho

IPC: H01L21/336 ,  H01L21/822 ,  H01L27/11556 ,  H01L27/11597 ,  H01L27/11578 ,  H01L27/1157 ,  H01L27/11551 ,  H01L29/792 ,  H01L29/788 ,  H01L21/28 ,  H01L21/8234 ,  H01L21/768 ,  H01L27/105 ,  H01L29/78 ,  H01L27/11582 ,  H01L49/02

Abstract: A vertical memory device may include a plurality of word lines spaced apart in a first direction, each extending in a second direction perpendicular to the first direction and having a first width in a third direction perpendicular to the first and second directions, a dummy word line over an uppermost word line, including an opening and having a portion thereof with the first width in the third direction, a first string selection line (SSL) and a second string selection line (SSL) over the dummy word line, the first and second SSLs being at substantially the same level along the first direction, each of the first and second SSLs having a second width less than the first width in the third direction, and a plurality of vertical channel structures, each through the word lines, the dummy word line, and one of the first and second SSLs.

公开(公告)号：US09490829B2

公开(公告)日：2016-11-08

申请号：US14244206

申请日：2014-04-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-Wook Han ,  Sung-Jun Lee ,  In-Yup Kang ,  Thomas Byunghak Cho ,  Joon-Hee Lee ,  Si-Bum Jun ,  Jong-Won Choi

IPC: H03L7/10 ,  H03L7/197

CPC classification number: H03L7/104 ,  H03L7/1976 ,  H03L2207/05

Abstract: An electronic device for synthesizing a frequency is provided. The electronic device includes a bank changer configured to output a channel code corresponding to a reference frequency signal and a feedback frequency signal, a channel code mapper configured to generate a changed channel code by applying an offset to the channel code output from the bank changer, and a voltage controlled oscillator configured to control a total capacitance of a plurality of capacitors based on the changed channel code and to oscillate a frequency dependent on the total capacitance.

Abstract translation: 提供了一种用于合成频率的电子装置。 电子设备包括：银行变换器，被配置为输出与参考频率信号和反馈频率信号相对应的信道码;频道码映射器，被配置为通过对从银行变换器输出的信道码施加偏移来产生改变的信道码; 以及电压控制振荡器，其被配置为基于改变的信道码来控制多个电容器的总电容，并且根据总电容振荡频率。