公开(公告)号：US20210408241A1

公开(公告)日：2021-12-30

申请号：US17471244

申请日：2021-09-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seojin JEONG ,  Jinyeong JOE ,  Seokhoon KIM ,  Jeongho YOO ,  Seung Hun LEE ,  Sihyung LEE

IPC: H01L29/16 ,  H01L29/10 ,  H01L29/04 ,  H01L29/167 ,  H01L29/36 ,  H01L27/092 ,  H01L29/06 ,  H01L21/8238 ,  H01L21/762 ,  H01L29/66 ,  H01L29/08

Abstract: A semiconductor device includes a substrate, a device isolation layer on the substrate, the device isolation layer defining a first active pattern, a pair of first source/drain patterns on the first active pattern, the pair of first source/drain patterns being spaced apart from each other in a first direction, and each of the pair of first source/drain patterns having a maximum first width in the first direction, a first channel pattern between the pair of first source/drain patterns, a gate electrode on the first channel pattern and extends in a second direction intersecting the first direction, and a first amorphous region in the first active pattern, the first amorphous region being below at least one of the pair of first source/drain patterns, and having a maximum second width in the first direction that is less than the maximum first width.

公开(公告)号：US20230326970A1

公开(公告)日：2023-10-12

申请号：US18050684

申请日：2022-10-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Namkyu CHO ,  Seokhoon KIM ,  Jeongho YOO ,  Choeun LEE ,  Pankwi PARK ,  Dongsuk SHIN

IPC: H01L29/08 ,  H01L29/786 ,  H01L27/092 ,  H01L29/66 ,  H01L29/775 ,  H01L29/40 ,  H01L29/423 ,  H01L29/417 ,  H01L21/8238

CPC classification number: H01L29/0847 ,  H01L29/78696 ,  H01L27/092 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/401 ,  H01L29/42392 ,  H01L29/41733 ,  H01L29/41783 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823871 ,  H01L29/0673

Abstract: A semiconductor device includes a substrate including a first active pattern, a first channel pattern on the first active pattern, the first channel pattern including first, second, and third semiconductor patterns spaced apart from one another and vertically stacked, a first source/drain pattern connected to the first to third semiconductor patterns, and a gate electrode on the first to third semiconductor patterns. The first source/drain pattern includes a first protrusion protruding toward the first semiconductor pattern, a second protrusion protruding toward the second semiconductor pattern, and a third protrusion protruding toward the third semiconductor pattern. A width of the second protrusion is greater than a width of the first protrusion. A width of the third protrusion is greater than the width of the second protrusion.

公开(公告)号：US20230223405A1

公开(公告)日：2023-07-13

申请号：US18122253

申请日：2023-03-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Minhee CHOI ,  Keunhwi CHO ,  Myunggil KANG ,  Seokhoon KIM ,  Dongwon KIM ,  Pankwi PARK ,  Dongsuk SHIN

IPC: H01L29/08 ,  H01L29/06 ,  H01L29/161 ,  H01L29/167 ,  H01L29/423 ,  H01L29/775 ,  H01L21/02 ,  H01L29/66

CPC classification number: H01L29/0847 ,  H01L29/0673 ,  H01L29/161 ,  H01L29/167 ,  H01L29/42392 ,  H01L29/775 ,  H01L21/02532 ,  H01L21/02579 ,  H01L21/0262 ,  H01L29/66439

Abstract: An integrated circuit device includes a fin-type active area along a first horizontal direction on a substrate, a device isolation layer on opposite sidewalls of the fin-type active area, a gate structure along a second horizontal direction crossing the first horizontal direction, the gate structure being on the fin-type active area and on the device isolation layer, and a source/drain area on the fin-type active area, the source/drain area being adjacent to the gate structure, and including an outer blocking layer, an inner blocking layer, and a main body layer sequentially stacked on the fin-type active area, and each of the outer blocking layer and the main body layer including a Si1-xGex layer, where x≠0, and the inner blocking layer including a Si layer.

公开(公告)号：US20200020773A1

公开(公告)日：2020-01-16

申请号：US16452668

申请日：2019-06-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Min-Hee CHOI ,  Seokhoon KIM ,  Choeun LEE ,  Edward Namkyu CHO ,  Seung Hun LEE

IPC: H01L29/08 ,  H01L27/11 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/417 ,  H01L29/78

Abstract: A semiconductor device including a substrate including an active pattern; a gate electrode crossing the active pattern; a source/drain pattern adjacent to one side of the gate electrode and on an upper portion of the active pattern; an active contact electrically connected to the source/drain pattern; and a silicide layer between the source/drain pattern and the active contact, the source/drain pattern including a body part including a plurality of semiconductor patterns; and a capping pattern on the body part, the body part has a first facet, a second facet on the first facet, and a corner edge defined where the first facet meets the second facet, the corner edge extending parallel to the substrate, the capping pattern covers the second facet of the body part and exposes the corner edge, and the silicide layer covers a top surface of the body part and a top surface of the capping pattern.

公开(公告)号：US20190139811A1

公开(公告)日：2019-05-09

申请号：US15869718

申请日：2018-01-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sunguk Jang ,  Seokhoon KIM ,  Seung Hun LEE ,  Yang XU ,  Jeongho YOO ,  Jongryeol YOO ,  Youngdae CHO

IPC: H01L21/762 ,  H01L29/66 ,  H01L29/423 ,  H01L29/165 ,  H01L21/02 ,  H01L21/225

Abstract: Semiconductor devices and methods of forming the same are provided. The methods may implanting dopants into a substrate to form a preliminary impurity region and heating the substrate to convert the preliminary impurity region into an impurity region. Heating the substrate may be performed at an ambient temperature of from about 800° C. to about 950° C. for from about 20 min to about 50 min. The method may also include forming first and second trenches in the impurity region to define an active tin and forming a first isolation layer and a second isolation layer in the first and second trenches, respectively. The first and second isolation layers may expose opposing sides of the active fin. The method may further include forming a gate insulation layer extending on the opposing sides and an upper surface of the active fin and forming a gate electrode traversing the active fin

公开(公告)号：US20230207626A1

公开(公告)日：2023-06-29

申请号：US17874945

申请日：2022-07-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Namkyu CHO ,  Sanggil LEE ,  Seokhoon KIM ,  Pankwi PARK

IPC: H01L29/08 ,  H01L29/66 ,  H01L29/775 ,  H01L29/06 ,  H01L29/423 ,  H01L29/417 ,  H01L29/786 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/40

CPC classification number: H01L29/0847 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/41775 ,  H01L29/78684 ,  H01L27/092 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/401 ,  H01L29/78696

Abstract: A semiconductor device may include a substrate including center and edge regions, active patterns on the substrate, channel patterns on the active patterns, source/drain patterns connected to the channel patterns, and gate electrodes on the channel patterns. Each of the source/drain patterns may include a buffer layer in contact with a corresponding one of the channel patterns and a main layer on the buffer layer. The main layer of each of the source/drain patterns may include first and second semiconductor layers, which may be sequentially stacked and contain germanium. A concentration of the germanium in the first semiconductor layer may be higher on the center region than on the edge region, and a concentration of the germanium in the second semiconductor layer may be lower on the center region than on the edge region.

公开(公告)号：US20220190112A1

公开(公告)日：2022-06-16

申请号：US17686700

申请日：2022-03-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Min-Hee CHOI ,  Seokhoon KIM ,  Choeun LEE ,  Edward Namkyu CHO ,  Seung Hun LEE

IPC: H01L29/08 ,  H01L27/11 ,  H01L27/092 ,  H01L29/78 ,  H01L21/8238 ,  H01L29/417 ,  H01L27/108

Abstract: A semiconductor device including a substrate including an active pattern; a gate electrode crossing the active pattern; a source/drain pattern adjacent to one side of the gate electrode and on an upper portion of the active pattern; an active contact electrically connected to the source/drain pattern; and a silicide layer between the source/drain pattern and the active contact, the source/drain pattern including a body part including a plurality of semiconductor patterns; and a capping pattern on the body part, the body part has a first facet, a second facet on the first facet, and a corner edge defined where the first facet meets the second facet, the corner edge extending parallel to the substrate, the capping pattern covers the second facet of the body part and exposes the corner edge, and the silicide layer covers a top surface of the body part and a top surface of the capping pattern.

公开(公告)号：US20220102498A1

公开(公告)日：2022-03-31

申请号：US17546690

申请日：2021-12-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seokhoon KIM ,  Dongmyoung Kim ,  Kanghun Moon ,  Hyunkwan Yu ,  Sanggil Lee ,  Seunghun Lee ,  Sihyung Lee ,  Choeun Lee ,  Edward Namkyu Cho ,  Yang Xu

IPC: H01L29/08 ,  H01L29/78 ,  H01L27/088 ,  H01L29/06

Abstract: A semiconductor device includes a substrate, a fin structure on the substrate, a gate structure on the fin structure, a gate spacer on at least on side surface of the gate structure, and a source/drain structure on the fin structure, wherein a topmost portion of a bottom surface of the gate spacer is lower than a topmost portion of a top surface of the fin structure, and a topmost portion of a top surface of the source/drain structure is lower than the topmost portion of the top surface of the fin structure.

公开(公告)号：US20150214370A1

公开(公告)日：2015-07-30

申请号：US14491117

申请日：2014-09-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinbum KIM ,  Bonyoung KOO ,  Seokhoon KIM ,  Chul KIM ,  Kwan Heum LEE ,  Byeongchan LEE ,  Sujin JUNG

IPC: H01L29/78 ,  H01L29/08

CPC classification number: H01L29/0847 ,  H01L21/30608 ,  H01L21/3065 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: A semiconductor device includes a substrate provided with an active pattern; a gate structure provided on the active pattern to cross the active pattern; and source/drain regions provided at both sides of the gate structure. The active pattern includes a first region below the gate structure and second regions at both sides of the gate structure. A top surface of each of the second regions is lower than that of the first region. The source/drain regions are provided on the second regions, respectively, and each of the source/drain regions covers partially both sidewalls of each of the second regions.

Abstract translation: 半导体器件包括具有活性图案的衬底; 栅极结构，设置在所述有源图案上以穿过所述有源图案; 以及设置在栅极结构的两侧的源极/漏极区域。 有源图案包括栅极结构下方的第一区域和栅极结构两侧的第二区域。 每个第二区域的顶表面低于第一区域的顶表面。 源极/漏极区域分别设置在第二区域上，并且每个源极/漏极区域部分地覆盖每个第二区域的两个侧壁。

公开(公告)号：US20240243188A1

公开(公告)日：2024-07-18

申请号：US18513759

申请日：2023-11-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyohoon BYEON ,  Seokhoon KIM ,  Unki KIM ,  Pankwi PARK ,  Sungkeun LIM ,  Yuyeong JO

IPC: H01L29/66 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/66545 ,  H01L21/823425 ,  H01L21/823475 ,  H01L27/088 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78696

Abstract: An integrated circuit device includes: a rear wiring structure; an insulating substrate including fin structures disposed on the rear wiring structure and extending in a first horizontal direction; a device isolation layer disposed between the fin structures; a lower insulating layer covering the fin structures; gate structures extending in a second horizontal direction crossing the first horizontal direction; a plurality of nanosheet stacks disposed on the lower insulating layer; a first source/drain region disposed on the insulating substrate and including a body portion and a vertical extension portion, wherein the body portion is disposed between the plurality of nanosheet stacks, and the vertical extension portion passes through the lower insulating layer and through some of the fin structures; a semiconductor epitaxial structure at least partially surrounding the vertical extension portion of the first source/drain region; and a lower contact connecting the semiconductor epitaxial structure with the rear wiring structure.