公开(公告)号：US08921993B2

公开(公告)日：2014-12-30

申请号：US14153327

申请日：2014-01-13

Applicant: Samsung Electronics Co., Ltd

Inventor： In-Ho Choi ,  Yong-Hoon Kim ,  Seong-Ho Shin

IPC: H01L23/52 ,  H01L23/552

CPC classification number: H01L23/552 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/2929 ,  H01L2224/29339 ,  H01L2224/29387 ,  H01L2224/29388 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/1615 ,  H01L2924/16251 ,  H01L2924/16724 ,  H01L2924/16747 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/00

Abstract: A semiconductor package includes a substrate, a semiconductor chip located on a top surface of the substrate, signal lines formed on the top surface of the substrate and configured to allow different types of signals to input/output thereto/therefrom, a ground line unit formed on the top surface of the substrate and configured to divide the signal lines into signal lines to/from which the same types of signals are input/output to be isolated from one another, barrier walls configured to contact the ground line unit, and a heat dissipation unit disposed on the semiconductor chip, wherein the ground line unit includes diagonal ground lines located in diagonal directions of the substrate about the semiconductor chip, and the heat dissipation unit includes a thermal interface material (TIM) located on a top surface of the semiconductor chip, and a heat dissipation plate configured to cover the TIM and the substrate.

Abstract translation: 半导体封装包括衬底，位于衬底的顶表面上的半导体芯片，形成在衬底的顶表面上并被配置为允许不同类型的信号从其输入/输出的信号线，形成的接地线单元 在基板的顶表面上，并且将信号线分成信号线，以使相同类型的信号被输入/输出为彼此隔离的信号线，被配置为接触地线单元的阻挡壁和热量 设置在半导体芯片上的散热单元，其中接地线单元包括位于半导体芯片周围的基板的对角线方向的对角线，而散热单元包括位于半导体芯片顶表面上的热界面材料（TIM） 芯片，以及配置成覆盖TIM和基板的散热板。

公开(公告)号：US09627126B2

公开(公告)日：2017-04-18

申请号：US14255237

申请日：2014-04-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyun-Jong Moon ,  Bok-Sik Myung ,  Seong-Ho Shin

IPC: H05K1/18 ,  H01F27/28 ,  H05K1/16 ,  H05K1/02

CPC classification number: H01F27/2804 ,  H01F2027/2809 ,  H05K1/024 ,  H05K1/0298 ,  H05K1/165

Abstract: A printed circuit board (PCB) includes an insulating substrate, a plurality of copper foil pattern layers and a plurality of insulating adhesive sheets sequentially stacked on an upper side of the insulating substrate and a lower side of the insulating substrate, an inductor included in the copper foil pattern layer disposed on the upper side of the insulating substrate, a grounding element included in the copper foil pattern layer disposed on the lower side of the insulating substrate, and a single through hole penetrating the insulating substrate and the insulating adhesive sheets. The single through hole is disposed between the inductor and the grounding element.

公开(公告)号：US09520387B2

公开(公告)日：2016-12-13

申请号：US14504972

申请日：2014-10-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yong-Hoon Kim ,  Hee-Seok Lee ,  Seong-Ho Shin ,  Se-Ho You ,  Yun-Hee Lee

IPC: H01L21/00 ,  H01L25/00 ,  H01L23/31 ,  H01L23/552 ,  H01L25/10 ,  H01L25/16 ,  H01L23/522 ,  H01L23/00

CPC classification number: H01L25/50 ,  H01L23/3128 ,  H01L23/5226 ,  H01L23/552 ,  H01L24/11 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L25/105 ,  H01L25/16 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45139 ,  H01L2224/48091 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2225/06568 ,  H01L2225/1023 ,  H01L2225/1052 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2225/1088 ,  H01L2924/00014 ,  H01L2924/01012 ,  H01L2924/07802 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1436 ,  H01L2924/1438 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/18161 ,  H01L2924/3025 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599

Abstract: A stacked package structure is provided. The stacked package structure includes a stacked package including a lower semiconductor package, an upper semiconductor package disposed on the lower semiconductor package and spaced a predetermined distance apart from the lower semiconductor package, an inter-package connecting portion electrically connecting the lower semiconductor package and the upper semiconductor package while supporting a space therebetween, and an insulation layer disposed at least outside the inter-package connecting portion and filling the space between the lower semiconductor package and the upper semiconductor package, and an electromagnetic shielding layer surrounding lateral and top surfaces of the stacked package.

Abstract translation: 提供堆叠的包装结构。 堆叠封装结构包括：堆叠封装，包括下半导体封装，设置在下半导体封装上并与下半导体封装隔开预定距离的上半导体封装;电连接下半导体封装和 上部半导体封装，同时支撑它们之间的空间，以及绝缘层，其至少设置在所述封装间连接部分的外部并填充所述下部半导体封装和所述上部半导体封装之间的空间，以及围绕所述下部半导体封装的横向和顶部表面的电磁屏蔽层 堆叠包装。

公开(公告)号：US20140264339A1

公开(公告)日：2014-09-18

申请号：US14132790

申请日：2013-12-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ji-Chul Kim ,  Hee-Jung Hwang ,  Seong-Ho Shin

IPC: F25B21/02 ,  H01L23/38 ,  H01L23/34

CPC classification number: F25B21/02 ,  F25B2321/0212 ,  H01L23/34 ,  H01L23/36 ,  H01L23/38 ,  H01L23/49816 ,  H01L2224/48091 ,  H01L2924/00014

Abstract: In a heat slug and a semiconductor package including the same, the heat slug includes a thermal conductive body having an active face and a dissipating face opposite to the active face, a dielectric layer covering the active face of the body, at least one thermoelectric element arranged on the dielectric layer and a conductive pattern arranged on the dielectric layer and electrically connected to the thermoelectric element. The electrical characteristics of the thermoelectric element are interacted with heat generated from a heat source.

Abstract translation: 在散热片和包括其的半导体封装件中，散热片包括导热体，其具有活性面和与有源面相反的散开面，覆盖主体的有源面的电介质层，至少一个热电元件 布置在电介质层上，并且布置在电介质层上并与电热元件电连接的导电图案。 热电元件的电气特性与从热源产生的热量相互作用。

公开(公告)号：US08981581B2

公开(公告)日：2015-03-17

申请号：US14190079

申请日：2014-02-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Heung-Kyu Kwon ,  Seong-Ho Shin ,  Yun-Seok Choi ,  Yong-Hoon Kim

IPC: H01L23/48 ,  H01L23/02 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L21/56 ,  H01L25/10 ,  H01L25/065

CPC classification number: H01L24/06 ,  H01L21/563 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49866 ,  H01L24/73 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/0401 ,  H01L2224/05554 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45139 ,  H01L2224/48227 ,  H01L2224/48229 ,  H01L2224/49175 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2225/06562 ,  H01L2225/06565 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00014

Abstract: A package stack structure may an upper package include an upper package substrate having a first edge and a second edge opposite to the first edge. The upper package substrate has a first region arranged near the first edge and a second region arranged near the second edge. A first upper semiconductor device is mounted on the upper package substrate. The package stack structure may also include a lower package having a lower package substrate and a lower semiconductor device. The lower package is connected to the upper package through a plurality of inter-package connectors. The plurality of the inter-package connectors may include first inter-package connectors configured to transmit data signals; second inter-package connectors configured to transmit address/control signals; third inter-package connectors configured to provide a supply voltage for an address/control circuit; and fourth inter-package connectors configured to provide a supply voltage for a data circuit.

Abstract translation: 封装堆叠结构可以是上封装包括具有第一边缘和与第一边缘相对的第二边缘的上封装基板。 上封装衬底具有布置在第一边缘附近的第一区域和布置在第二边缘附近的第二区域。 第一上半导体器件安装在上封装衬底上。 封装堆叠结构还可以包括具有下封装衬底和下半导体器件的下封装。 下封装通过多个封装间连接器连接到上封装。 多个包装间连接器可以包括被配置为传送数据信号的第一包装间连接器; 配置成发送地址/控制信号的第二串联连接器连接器; 第三组件间连接器，被配置为提供地址/控制电路的电源电压; 以及被配置为提供数据电路的电源电压的第四组件间连接器。

公开(公告)号：US20140362551A1

公开(公告)日：2014-12-11

申请号：US14255237

申请日：2014-04-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： HYUN-JONG MOON ,  Bok-Sik Myung ,  Seong-Ho Shin

IPC: H01F27/28 ,  H05K1/09 ,  H05K1/02

CPC classification number: H01F27/2804 ,  H01F2027/2809 ,  H05K1/024 ,  H05K1/0298 ,  H05K1/165

Abstract: A printed circuit board (PCB) includes an insulating substrate, a plurality of copper foil pattern layers and a plurality of insulating adhesive sheets sequentially stacked on an upper side of the insulating substrate and a lower side of the insulating substrate, an inductor included in the copper foil pattern layer disposed on the upper side of the insulating substrate, a grounding element included in the copper foil pattern layer disposed on the lower side of the insulating substrate, and a single through hole penetrating the insulating substrate and the insulating adhesive sheets. The single through hole is disposed between the inductor and the grounding element.

Abstract translation: 印刷电路板（PCB）包括绝缘基板，多个铜箔图形层和顺序堆叠在绝缘基板的上侧上的多个绝缘粘合片和绝缘基板的下侧，电感器包括在 布置在绝缘基板的上侧的铜箔图形层，设置在绝缘基板的下侧的铜箔图案层中的接地元件，以及贯穿绝缘基板和绝缘粘合片的单个通孔。 单个通孔设置在电感器和接地元件之间。