公开(公告)号：US20170148716A9

公开(公告)日：2017-05-25

申请号：US14817233

申请日：2015-08-04

Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.

Inventor： Ching-Wen Chiang ,  Kuang-Hsin Chen ,  Sheng-Li Lu ,  Hsien-Wen Chen

IPC: H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31

CPC classification number: H01L23/49838 ,  H01L21/486 ,  H01L21/56 ,  H01L21/561 ,  H01L21/568 ,  H01L23/13 ,  H01L23/3121 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/5389 ,  H01L24/19 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/18 ,  H01L2224/19 ,  H01L2224/20 ,  H01L2224/92144 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/15153 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012

Abstract: A met of fabricating an electronic package is provided, g: providing a carrier body haying a first surface formed with a plurality of recessed portions, and a second surface opposing the first surface and interconnecting with the recessed portions; forming on the first surface of the carrier body an electronic structure that has a plurality of conductive elements received in the recessed portions correspondingly; and removing a portion of the carrier body, with the conductive elements exposed from the second surface of the carrier body. Therefore, the carrier body is retained, and the fabrication cost is reduced since no temporary material is required. The present invention further provides the electronic package thus fabricated.

公开(公告)号：US09627307B2

公开(公告)日：2017-04-18

申请号：US14919867

申请日：2015-10-22

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Ching-Wen Chiang ,  Cheng-Hao Ciou ,  Cheng-Chieh Wu ,  Kuang-Hsin Chen ,  Hsien-Wen Chen

IPC: H01L23/31 ,  H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L23/538 ,  H01L23/00

CPC classification number: H01L23/49827 ,  H01L21/481 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/5389 ,  H01L23/562 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/24137 ,  H01L2224/24195 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73267 ,  H01L2224/82005 ,  H01L2224/82031 ,  H01L2224/82039 ,  H01L2224/83005 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/1815 ,  H01L2924/18162 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/3511 ,  H01L2924/37001 ,  H01L2224/83 ,  H01L2224/82

Abstract: A semiconductor package is provided, including: an insulating base body having a first surface with an opening and a second surface opposite to the first surface; an insulating extending body extending outward from an edge of the first surface of the insulating base body, wherein the insulating extending body is less in thickness than the insulating base body; an electronic element having opposite active and inactive surfaces and disposed in the opening with its inactive surface facing the insulating base body; a dielectric layer formed in the opening of the insulating base body and on the first surface of the insulating base body, the insulating extending body and the active surface of the electronic element; and a circuit layer formed on the dielectric layer and electrically connected to the electronic element. The configuration of the insulating layer of the invention facilitates to enhance the overall structural rigidity of the package.

公开(公告)号：US10236227B2

公开(公告)日：2019-03-19

申请号：US14998324

申请日：2015-12-24

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Lung-Shan Chuang ,  Ching-Wen Chiang ,  Tzung-Yen Wu ,  Chun-Hung Lu

IPC: H01L21/00 ,  H01L23/053 ,  H01L21/683 ,  H01L21/78 ,  H01L23/00 ,  H01L23/498 ,  H01L21/48 ,  H01L23/14

Abstract: An electronic package is provided, including a circuit portion, an electronic element disposed on the circuit portion and a lid member disposed on the circuit portion to cover the electronic element. A separation portion is formed between the lid member and the electronic element. The lid member facilitates to prevent warping of the overall package structure. The invention further provides a method for fabricating the electronic package.

公开(公告)号：US20160148873A1

公开(公告)日：2016-05-26

申请号：US14833586

申请日：2015-08-24

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Ching-Wen Chiang ,  Hsien-Wen Chen ,  Kuang-Hsin Chen ,  Chung-Chih Yen ,  Wei-Jen Chang

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/768

CPC classification number: H01L23/5384 ,  H01L23/147 ,  H01L23/15 ,  H01L23/5389 ,  H01L24/00 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2924/15153 ,  H01L2924/157 ,  H01L2924/15788 ,  H01L2924/3511 ,  H01L2924/37001

Abstract: A method for fabricating an electronic package is provided, which includes the steps of: providing a substrate having a cavity and a first via hole; disposing an electronic element in the cavity; forming a dielectric layer on the substrate and the electronic element; forming a circuit layer on the dielectric layer and forming a first conductive portion in the first via hole; forming on the substrate a second via hole communicating with the first via hole, the first and second via holes constituting a through hole; and forming a second conductive portion in the second via hole, the first and second conductive portions constituting a conductor. Since the through hole is formed through a two-step process, the invention can reduce the depth of the via holes and therefore perform laser drilling or etching processes with reduced energy, thereby avoiding damage of the conductive portions and improving the product reliability.

Abstract translation: 提供一种制造电子封装的方法，其包括以下步骤：提供具有空腔和第一通孔的基板; 将电子元件放置在空腔中; 在所述基板和所述电子元件上形成介电层; 在所述电介质层上形成电路层，并在所述第一通孔中形成第一导电部分; 在所述基板上形成与所述第一通孔连通的第二通孔，所述第一通孔和第二通孔构成通孔; 以及在所述第二通孔中形成第二导电部分，所述第一和第二导电部分构成导体。 由于通孔是通过两步法形成的，所以本发明可以减小通孔的深度，从而能够以较低的能量进行激光打孔或蚀刻处理，从而避免导电部的损坏，提高产品的可靠性。

公开(公告)号：US20160133556A1

公开(公告)日：2016-05-12

申请号：US14919867

申请日：2015-10-22

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Ching-Wen Chiang ,  Cheng-Hao Ciou ,  Cheng-Chieh Wu ,  Kuang-Hsin Chen ,  Hsien-Wen Chen

IPC: H01L23/498 ,  H01L23/31 ,  H01L21/48 ,  H01L23/29

CPC classification number: H01L23/49827 ,  H01L21/481 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/5389 ,  H01L23/562 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/24137 ,  H01L2224/24195 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73267 ,  H01L2224/82005 ,  H01L2224/82031 ,  H01L2224/82039 ,  H01L2224/83005 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/1815 ,  H01L2924/18162 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/3511 ,  H01L2924/37001 ,  H01L2224/83 ,  H01L2224/82

Abstract: A semiconductor package is provided, including: an insulating base body having a first surface with an opening and a second surface opposite to the first surface; an insulating extending body extending outward from an edge of the first surface of the insulating base body, wherein the insulating extending body is less in thickness than the insulating base body; an electronic element having opposite active and inactive surfaces and disposed in the opening with its inactive surface facing the insulating base body; a dielectric layer formed in the opening of the insulating base body and on the first surface of the insulating base body, the insulating extending body and the active surface of the electronic element; and a circuit layer formed on the dielectric layer and electrically connected to the electronic element. The configuration of the insulating layer of the invention facilitates to enhance the overall structural rigidity of the package.

Abstract translation: 提供了一种半导体封装，包括：绝缘基体，具有带有开口的第一表面和与第一表面相对的第二表面; 绝缘延伸体，其从所述绝缘基体的所述第一表面的边缘向外延伸，其中所述绝缘延伸体的厚度小于所述绝缘基体的厚度; 电子元件具有相对的有源和非活性表面并且设置在开口中，其非活性表面面向绝缘基体; 形成在所述绝缘基体的开口部和所述绝缘基体的所述第一面上的电介质层，所述绝缘延伸体和所述电子元件的有源面; 以及形成在电介质层上并电连接到电子元件的电路层。 本发明的绝缘层的结构有助于提高封装的整体结构刚度。

公开(公告)号：US10199320B2

公开(公告)日：2019-02-05

申请号：US15784782

申请日：2017-10-16

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Ching-Wen Chiang ,  Kuang-Hsin Chen ,  Sheng-Li Lu ,  Hsien-Wen Chen

IPC: H01L23/498 ,  H01L21/56 ,  H01L23/00 ,  H01L21/48 ,  H01L23/31 ,  H01L23/538 ,  H01L23/13

Abstract: A method of fabricating an electronic package is provided, including: providing a carrier body having a first surface formed with a plurality of recessed portions, and a second surface opposing the first surface and interconnecting with the recessed portions; forming on the first surface of the carrier body an electronic structure that has a plurality of conductive elements received in the recessed portions correspondingly; and removing portion of the carrier body, with the conductive elements exposed from the second surface of the carrier body. Therefore, the carrier body is retained, and the fabrication cost is reduced since temporary material is required. The present invention further provides the electronic package thus fabricated.

公开(公告)号：US20180138140A1

公开(公告)日：2018-05-17

申请号：US15867008

申请日：2018-01-10

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Hsin-Ta Lin ,  Ching-Wen Chiang

IPC: H01L23/00 ,  H01L21/48 ,  H01L23/498 ,  H01L23/31

CPC classification number: H01L24/13 ,  H01L21/4846 ,  H01L23/3192 ,  H01L23/49816 ,  H01L23/49894 ,  H01L24/11 ,  H01L2224/1145 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/13016 ,  H01L2224/13025 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2924/2064

Abstract: A substrate structure is provided, which includes: a substrate body having a plurality of conductive pads; an insulating layer formed on the substrate body and exposing the conductive pads; a plurality of conductive vias formed in the insulating layer and electrically connected to the conductive pads; a plurality of circuits formed on the conductive vias and in the insulating layer, wherein the circuits are greater in width than the conductive vias; and a plurality of conductive posts formed on the circuits and the insulating layer, wherein each of the conductive posts has a width greater than or equal to that of each of the circuits. The conductive vias, the circuits and the conductive posts are integrally formed. As such, micro-chips or fine-pitch conductive pads can be electrically connected to the substrate structure in a flip-chip manner.

公开(公告)号：US20180040550A1

公开(公告)日：2018-02-08

申请号：US15784782

申请日：2017-10-16

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Ching-Wen Chiang ,  Kuang-Hsin Chen ,  Sheng-Li Lu ,  Hsien-Wen Chen

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/538 ,  H01L21/56 ,  H01L23/31

CPC classification number: H01L23/49838 ,  H01L21/486 ,  H01L21/56 ,  H01L21/561 ,  H01L21/568 ,  H01L23/13 ,  H01L23/3121 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/5389 ,  H01L24/19 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/18 ,  H01L2224/19 ,  H01L2224/20 ,  H01L2224/92144 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/15153 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/181 ,  H01L2924/00012

Abstract: A method of fabricating an electronic package is provided, including: providing a carrier body having a first surface formed with a plurality of recessed portions, and a second surface opposing the first surface and interconnecting with the recessed portions; forming on the first surface of the carrier body an electronic structure that has a plurality of conductive elements received in the recessed portions correspondingly; and removing portion of the carrier body, with the conductive elements exposed from the second surface of the carrier body. Therefore, the carrier body is retained, and the fabrication cost is reduced since temporary material is required. The present invention further provides the electronic package thus fabricated.

公开(公告)号：US09818683B2

公开(公告)日：2017-11-14

申请号：US14817233

申请日：2015-08-04

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Ching-Wen Chiang ,  Kuang-Hsin Chen ,  Sheng-Li Lu ,  Hsien-Wen Chen

IPC: H01L23/48 ,  H01L23/498 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56

CPC classification number: H01L23/49838 ,  H01L21/486 ,  H01L21/56 ,  H01L21/561 ,  H01L21/568 ,  H01L23/13 ,  H01L23/3121 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/5389 ,  H01L24/19 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/18 ,  H01L2224/19 ,  H01L2224/20 ,  H01L2224/92144 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/15153 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012

Abstract: A met of fabricating an electronic package is provided, including: providing a carrier body haying a first surface formed with a plurality of recessed portions, and a second surface opposing the first surface and interconnecting with the recessed portions; forming on the first surface of the carrier body an electronic structure that has a plurality of conductive elements received in the recessed portions correspondingly; and removing a portion of the carrier body, with the conductive elements exposed from the second surface of the carrier body. Therefore, the carrier body is retained, and the fabrication cost is reduced since no temporary material is required. The present invention further provides the electronic package thus fabricated.

公开(公告)号：US20170194238A1

公开(公告)日：2017-07-06

申请号：US15069387

申请日：2016-03-14

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Ching-Wen Chiang ,  Hsin-Chih Wang ,  Chih-Yuan Shih ,  Shih-Ching Chen

IPC: H01L23/498 ,  H01L21/56 ,  H01L21/306 ,  H01L21/48 ,  H01L21/304

CPC classification number: H01L23/49827 ,  H01L21/304 ,  H01L21/306 ,  H01L21/486 ,  H01L21/563 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49833 ,  H01L2224/16225

Abstract: A substrate structure is provided, which includes: a substrate body having a first surface and a second surface opposite to the first surface; and a plurality of conductive posts disposed on the first surface of the substrate body and electrically connected to the substrate body. By replacing conventional through silicon vias (TSVs) with the conductive posts, the present disclosure greatly reduces the fabrication cost. The present disclosure further provides an electronic package having the substrate structure and a method for fabricating the electronic package.