公开(公告)号：US20150093702A1

公开(公告)日：2015-04-02

申请号：US14039140

申请日：2013-09-27

Applicant: Paul A. Nyhus ,  Eungnak Han ,  Swaminathan Sivakumar ,  Ernisse S. Putna

Inventor： Paul A. Nyhus ,  Eungnak Han ,  Swaminathan Sivakumar ,  Ernisse S. Putna

IPC: H01L21/768 ,  G03F7/039 ,  H01L21/027

CPC classification number: G03F7/0392 ,  B81C1/00428 ,  B81C2201/0149 ,  G03F7/0002 ,  G03F7/0045 ,  G03F7/038 ,  G03F7/039 ,  G03F7/11 ,  G03F7/16 ,  G03F7/2004 ,  G03F7/2037 ,  G03F7/26 ,  H01L21/0337 ,  H01L21/31058 ,  H01L21/32 ,  H01L21/3205 ,  H01L21/32139 ,  H01L21/76816

Abstract: Self-aligned via and plug patterning for back end of line (BEOL) interconnects are described. In an example, a structure for directed self-assembly includes a substrate and a block co-polymer structure disposed above the substrate. The block co-polymer structure has a polystyrene (PS) component and a polymethyl methacrylate (PMMA) component. One of the PS component or the PMMA component is photosensitive.

Abstract translation: 描述了用于后端（BEOL）互连的自对准通孔和插头图案。 在一个示例中，用于定向自组装的结构包括设置在衬底上方的衬底和嵌段共聚物结构。 嵌段共聚物结构具有聚苯乙烯（PS）组分和聚甲基丙烯酸甲酯（PMMA）组分。 PS组件或PMMA组件之一是光敏的。

公开(公告)号：US20140191372A1

公开(公告)日：2014-07-10

申请号：US13976077

申请日：2011-12-29

Applicant: Swaminathan Sivakumar ,  Elliot N. Tan

Inventor： Swaminathan Sivakumar ,  Elliot N. Tan

IPC: H01L21/02 ,  H01L29/06

CPC classification number: H01L21/02587 ,  H01L21/02658 ,  H01L21/0337 ,  H01L21/28 ,  H01L21/76816 ,  H01L29/0684 ,  Y10S438/942

Abstract: Spacer-based pitch division lithography techniques are disclosed that realize pitches with both variable line widths and variable space widths, using a single spacer deposition. The resulting feature pitches can be at or below the resolution limit of the exposure system being used, but they need not be, and may be further reduced (e.g., halved) as many times as desired with subsequent spacer formation and pattern transfer processes as described herein. Such spacer-based pitch division techniques can be used, for instance, to define narrow conductive runs, metal gates and other such small features at a pitch smaller than the original backbone pattern.

Abstract translation: 公开了使用单个间隔物沉积来实现具有可变线宽度和可变空间宽度的间距的基于间隔物的间距光刻技术。 所得到的特征间距可以处于或低于所使用的曝光系统的分辨率极限，但是它们不需要并且可以进一步减少（例如，减半），如所需的随后的间隔物形成和图案转移过程所需的多次 这里。 这种基于间隔物的螺距分割技术可以用于例如以比原始骨架图案小的间距来限定窄导电线，金属栅极和其它这样的小特征。

公开(公告)号：US20130320456A1

公开(公告)日：2013-12-05

申请号：US13995678

申请日：2011-12-22

Applicant: Oleg Golonzka ,  Swaminathan Sivakumar ,  Charles H. Wallace ,  Tahir Ghani

Inventor： Oleg Golonzka ,  Swaminathan Sivakumar ,  Charles H. Wallace ,  Tahir Ghani

IPC: H01L21/28 ,  H01L27/085

CPC classification number: H01L21/76897 ,  H01L21/28008 ,  H01L21/30625 ,  H01L21/32 ,  H01L21/76805 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823468 ,  H01L21/823475 ,  H01L21/823481 ,  H01L23/535 ,  H01L27/0207 ,  H01L27/088 ,  H01L27/0886 ,  H01L29/0653 ,  H01L29/66545

Abstract: Gate aligned contacts and methods of forming gate aligned contacts are described. For example, a method of fabricating a semiconductor structure includes forming a plurality of gate structures above an active region formed above a substrate. The gate structures each include a gate dielectric layer, a gate electrode, and sidewall spacers. A plurality of contact plugs is formed, each contact plug formed directly between the sidewall spacers of two adjacent gate structures of the plurality of gate structures. A plurality of contacts is formed, each contact formed directly between the sidewall spacers of two adjacent gate structures of the plurality of gate structures. The plurality of contacts and the plurality of gate structures are formed subsequent to forming the plurality of contact plugs.

Abstract translation: 描述门对齐的触点和形成栅极对准触点的方法。 例如，制造半导体结构的方法包括在形成在衬底上方的有源区上方形成多个栅极结构。 栅极结构各自包括栅极介电层，栅电极和侧壁间隔物。 形成多个接触插塞，每个接触插塞直接形成在多个门结构的两个相邻门结构的侧壁间隔件之间。 形成多个触点，每个触点直接形成在多个栅极结构的两个相邻栅极结构的侧壁间隔件之间。 在形成多个接触插塞之后形成多个触点和多个栅极结构。

公开(公告)号：US20090267175A1

公开(公告)日：2009-10-29

申请号：US12111702

申请日：2008-04-29

Applicant: Charles H. Wallace ,  Matthew Tingey ,  Swaminathan Sivakumar

Inventor： Charles H. Wallace ,  Matthew Tingey ,  Swaminathan Sivakumar

IPC: H01L21/308 ,  H01L27/00

CPC classification number: H01L21/308 ,  H01L21/0271 ,  H01L21/3086 ,  H01L21/3088

Abstract: Double patterning techniques and structures are generally described. In one example, a method includes depositing a first photoresist to a semiconductor substrate, forming a first integrated circuit (IC) pattern in the first photoresist, the first IC pattern comprising one or more trench structures, protecting the first IC pattern in the first photoresist from actions that form a second IC pattern in a second photoresist, depositing the second photoresist to the first IC pattern, and forming the second IC pattern in the second photoresist, the second IC pattern comprising one or more structures that are sufficiently close to the one or more trench structures of the first IC pattern to cause scumming of the second photoresist in the one or more trench structures of the first IC pattern.

Abstract translation: 通常描述双重图案形成技术和结构。 在一个实例中，一种方法包括将第一光致抗蚀剂沉积到半导体衬底，在第一光致抗蚀剂中形成第一集成电路（IC）图案，第一IC图案包括一个或多个沟槽结构，保护第一光致抗蚀剂中的第一IC图案 从在第二光致抗蚀剂中形成第二IC图案的动作，将第二光致抗蚀剂沉积到第一IC图案，以及在第二光致抗蚀剂中形成第二IC图案，第二IC图案包括一个或多个足够接近该一个的结构 或更多个沟槽结构，以使第一IC图案的一个或多个沟槽结构中的第二光致抗蚀剂浮渣。

公开(公告)号：US07312155B2

公开(公告)日：2007-12-25

申请号：US10819790

申请日：2004-04-07

Applicant: Valery M. Dubin ,  Swaminathan Sivakumar ,  Andrew A. Berlin ,  Mark Bohr

Inventor： Valery M. Dubin ,  Swaminathan Sivakumar ,  Andrew A. Berlin ,  Mark Bohr

IPC: H01L21/44 ,  H01L21/00 ,  H01L21/336

CPC classification number: H01L21/76838 ,  B82Y10/00 ,  H01L21/76852 ,  H01L51/0021 ,  H01L51/0048 ,  H01L51/0052 ,  H01L2221/1094 ,  Y10S977/742 ,  Y10S977/936

Abstract: A nano-electrode or nano-wire may be etched centrally to form a gap between nano-electrode portions. The portions may ultimately constitute a single electron transistor. The source and drain formed from the electrode portions are self-aligned with one another. Using spacer technology, the gap between the electrodes may be made very small.

Abstract translation: 可以将纳米电极或纳米线中心蚀刻以形成纳米电极部分之间的间隙。 这些部分可以最终构成单个电子晶体管。 由电极部分形成的源极和漏极彼此自对准。 使用间隔技术，可以使电极之间的间隙非常小。

公开(公告)号：US20070231748A1

公开(公告)日：2007-10-04

申请号：US11393096

申请日：2006-03-29

Applicant: Swaminathan Sivakumar ,  Charles Wallace

Inventor： Swaminathan Sivakumar ,  Charles Wallace

IPC: G03F7/26

CPC classification number: H01L21/31144 ,  H01L21/0337 ,  H01L21/76816

Abstract: A method for forming two trenches with tight end-to-end spacing in a dielectric layer begins with providing a substrate having a dielectric layer. A hard-mask layer is deposited on the dielectric layer and a first photoresist layer is deposited on the hard-mask layer. The first photoresist layer is patterned to form an extended trench in the first photoresist layer. The hard-mask layer is then etched using the first photoresist layer as a mask to form an extended trench in the hard-mask layer. Next, a second photoresist layer is deposited on the hard-mask layer and patterned to form a resist line that intersects the extended trench. The resist line divides the extended trench into two separate trenches. The dielectric layer is then etched using the hard-mask layer and the resist line as a mask, thereby forming two trenches in the dielectric layer with end-to-end separation that corresponds to the resist line width.

Abstract translation: 在电介质层中形成具有紧密端到端间隔的两个沟槽的方法开始于提供具有介电层的衬底。 在介电层上沉积硬掩模层，并且在硬掩模层上沉积第一光致抗蚀剂层。 图案化第一光致抗蚀剂层以在第一光致抗蚀剂层中形成延伸的沟槽。 然后使用第一光致抗蚀剂层作为掩模蚀刻硬掩模层，以在硬掩模层中形成延伸的沟槽。 接下来，将第二光致抗蚀剂层沉积在硬掩模层上并图案化以形成与延伸沟槽相交的抗蚀剂线。 抗蚀剂线将扩展沟槽分成两个独立的沟槽。 然后使用硬掩模层和抗蚀剂线作为掩模来蚀刻电介质层，从而在对应于抗蚀剂线宽度的端对端分离中在电介质层中形成两个沟槽。

公开(公告)号：US20060051956A1

公开(公告)日：2006-03-09

申请号：US11262247

申请日：2005-10-28

Applicant: Swaminathan Sivakumar

Inventor： Swaminathan Sivakumar

IPC: H01L21/4763 ,  H01L21/302 ,  H01L21/44

CPC classification number: G03F7/095 ,  G03F7/091 ,  H01L21/0276

Abstract: A semiconductor wafer may be coated with an imageable anti-reflective coating. As a result, the coating may be removed using the same techniques used to remove overlying photoresists. This may overcome the difficulty of etching anti-reflective coatings using standard etches because of their poor selectivity to photoresist and the resulting propensity to cause integrated circuit defects arising from anti-reflective coating remnants.

Abstract translation: 可以用可成像的抗反射涂层涂覆半导体晶片。 结果，可以使用用于去除覆盖的光致抗蚀剂的相同技术去除涂层。 这可以克服使用标准蚀刻来蚀刻抗反射涂层的难度，因为它们对光致抗蚀剂的选择性差，并导致由抗反射涂层残留物引起集成电路缺陷的倾向。

公开(公告)号：US20050147928A1

公开(公告)日：2005-07-07

申请号：US10750053

申请日：2003-12-30

Applicant: Rex Frost ,  Swaminathan Sivakumar

Inventor： Rex Frost ,  Swaminathan Sivakumar

IPC: G03F7/40

CPC classification number: G03F7/40

Abstract: The present invention relates to the reduction of critical dimensions and the reduction of feature sizes in manufacturing integrated circuits. Specifically, the method controls photoresist flow rates to develop critical dimensions beyond the resolution limits of the photoresist material used, and the limits of lithographic tool sets. The resist material characteristics are modified by exposing the resist pattern to either electrons, photons, or ions. The exposure modifies the glass transition temperature, cross linking characteristics, decomposition temperature, or molecular weight of the resist material. The post-exposure resist is then easier to control during a subsequent reflow process to reduce the hole size or line size of the patterned resist.

Abstract translation: 本发明涉及减小制造集成电路中的关键尺寸和减小特征尺寸。 具体地说，该方法控制光致抗蚀剂的流速，以发展超出所使用的光致抗蚀剂材料的分辨率极限以及光刻工具组的极限的关键尺寸。 通过将抗蚀剂图案暴露于电子，光子或离子来修饰抗蚀剂材料特性。 曝光改变抗蚀剂材料的玻璃化转变温度，交联特性，分解温度或分子量。 在后续回流工艺中，后曝光抗蚀剂更容易控制，以减小图案化抗蚀剂的孔尺寸或线尺寸。

公开(公告)号：US09054215B2

公开(公告)日：2015-06-09

申请号：US13719113

申请日：2012-12-18

Applicant: Paul A. Nyhus ,  Swaminathan Sivakumar

Inventor： Paul A. Nyhus ,  Swaminathan Sivakumar

IPC: H01L21/8234 ,  H01L29/78 ,  H01L29/775 ,  H01L29/66 ,  B82Y10/00 ,  B82Y40/00 ,  H01L29/423 ,  H01L29/06 ,  H01L29/16

CPC classification number: H01L21/823487 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/02642 ,  H01L21/28123 ,  H01L21/30625 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823437 ,  H01L27/088 ,  H01L29/0676 ,  H01L29/16 ,  H01L29/42376 ,  H01L29/42392 ,  H01L29/517 ,  H01L29/66666 ,  H01L29/66742 ,  H01L29/775 ,  H01L29/7827 ,  H01L29/78618 ,  H01L29/78642 ,  H01L29/78651 ,  H01L29/78684 ,  H01L29/78696

Abstract: Directed self-assembly (DSA) material, or di-block co-polymer, to pattern features that ultimately define a channel region a gate electrode of a vertical nanowire transistor, potentially based on one lithographic operation. In embodiments, DSA material is confined within a guide opening patterned using convention lithography. In embodiments, channel regions and gate electrode materials are aligned to edges of segregated regions within the DSA material.

Abstract translation: 定向自组装（DSA）材料或二嵌段共聚物可能基于一个光刻操作来最终限定垂直纳米线晶体管的栅电极的通道区域的特征。 在实施例中，DSA材料被限制在使用常规光刻图案化的引导开口内。 在实施例中，沟道区域和栅电极材料与DSA材料内的分离区域的边缘对准。

公开(公告)号：US20140017899A1

公开(公告)日：2014-01-16

申请号：US13976090

申请日：2011-12-29

Applicant: Charles H. Wallace ,  Swaminathan Sivakumar ,  Matthew L. Tingey ,  Chanaka D. Munasinghe ,  Nadia M. Rahhal-Orabi

Inventor： Charles H. Wallace ,  Swaminathan Sivakumar ,  Matthew L. Tingey ,  Chanaka D. Munasinghe ,  Nadia M. Rahhal-Orabi

IPC: H01L21/308

CPC classification number: H01L21/3088 ,  H01L21/0337

Abstract: Techniques are disclosed for double patterning of a lithographic feature using a barrier layer between the pattern layers. In some cases, the techniques may be implemented with double patterning of a one- or two-dimensional photolithographic feature, for example. In some embodiments, the barrier layer is deposited to protect a first photoresist pattern prior to application of a second photoresist pattern thereon and/or to tailor (e.g., shrink) one or more of the critical dimensions of a trench, hole, or other etchable geometric feature to be formed in a substrate or other suitable surface via lithographic processes. In some embodiments, the techniques may be implemented to generate/print small features (e.g., less than or equal to about 100 nm) including one- and two-dimensional features/structures of varying complexity.

Abstract translation: 公开了使用图案层之间的阻挡层对光刻特征进行双重图案化的技术。 在一些情况下，例如，可以通过双图案化一维或二维光刻特征来实现这些技术。 在一些实施例中，沉积阻挡层以在施加第二光致抗蚀剂图案之前保护第一光致抗蚀剂图案和/或定制（例如，收缩）沟槽，孔或其它可蚀刻的一个或多个临界尺寸 通过光刻工艺在衬底或其它合适的表面中形成的几何特征。 在一些实施例中，可以实施技术来生成/打印包括不同复杂度的一维和二维特征/结构的小特征（例如，小于或等于约100nm）。