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公开(公告)号：US20230273370A1
公开(公告)日：2023-08-31
申请号：US17866335
申请日：2022-07-15
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Cheng-Tse TANG , Chewn-Pu JOU
CPC classification number: G02B6/124 , G02B6/12011 , G02B6/34 , G02B6/136 , G02B2006/12107
Abstract: A device includes an optical isolator disposed between adjacent optical waveguides along a direction. The optical isolator has vertical or horizontal dimensions that are different than at least one of the optical waveguides. The vertical and horizontal dimensions are greater than vertical and horizontal dimensions of at least one of the waveguides. In various embodiments, the structure of the optical isolator can be a planar structure, a columnar periodic structure, or a grating structure. The material of the optical isolator can be a metallic material or a dielectric material. In some embodiments, the optical isolator and the optical waveguides are used to enhance the performance of an optical multiplexing device.
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公开(公告)号：US20220386451A1
公开(公告)日：2022-12-01
申请号：US17884418
申请日：2022-08-09
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor： Jiun-Yi WU , Chien-Hsun LEE , Chewn-Pu JOU , Fu-Lung HSUEH
IPC: H05K1/02 , H01L21/768 , H01L21/48 , H01L23/498 , H01L23/552 , H05K1/11 , H05K3/00 , H05K3/40 , H05K3/42
Abstract: An interconnect structure includes a first conductor, a second conductor, a dielectric block, a substrate, and a pair of conductive lines. The first conductor and the second conductor form a differential pair design. The dielectric block surrounds the first conductor and the second conductor. The first conductor is separated from the second conductor by the dielectric block. The substrate surrounds the dielectric block and is spaced apart from the first conductor and the second conductor. The pair of conductive lines is connected to the first conductor and the second conductor, respectively, and extends along a top surface of the dielectric block and a top surface of the substrate.
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公开(公告)号：US20210072615A1
公开(公告)日：2021-03-11
申请号：US16952602
申请日：2020-11-19
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Huan-Neng CHEN , Chewn-Pu JOU , Lan-Chou CHO , Feng-Wei KUO
Abstract: In an embodiment, a phase shifter includes: a light input end; a light output end; a p-type semiconductor material, and an n-type semiconductor material contacting the p-type semiconductor material along a boundary area, wherein the boundary area is greater than a length from the light input end to the light output end multiplied by a core width of the phase shifter.
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公开(公告)号：US20210007215A1
公开(公告)日：2021-01-07
申请号：US17025887
申请日：2020-09-18
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor： Jiun-Yi WU , Chien-Hsun LEE , Chewn-Pu JOU , Fu-Lung HSUEH
IPC: H05K1/02 , H01L21/768 , H01L21/48 , H01L23/498 , H01L23/552 , H05K1/11 , H05K3/00 , H05K3/40 , H05K3/42
Abstract: An interconnect structure includes a substrate, a dielectric block, and a conductor. The dielectric block is in the substrate. A dielectric constant of the dielectric block is smaller than a dielectric constant of the substrate, and the dielectric block and the substrate have substantially the same thickness. The conductor includes a first portion extending from a top surface to a bottom surface of the dielectric block and a second portion extending along and contacting the top surface of the dielectric block.
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公开(公告)号：US20160294400A1
公开(公告)日：2016-10-06
申请号：US14990583
申请日：2016-01-07
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor： Feng-Wei KUO , Chewn-Pu JOU , Huan-Neng CHEN , Kuang-Kai YEN , Lan-Chou CHO , Robert Bogdan STASZEWSKI , Tsung-Hsiung LEE
CPC classification number: H03L7/0991 , H03L7/00 , H03L7/0802 , H03L7/085 , H03L7/18 , H03L2207/50
Abstract: A circuit and a method are disclosed herein. The circuit includes a digitally controlled oscillator and a detector. The digitally controlled oscillator is configured to generate an oscillator signal according to an oscillator tuning word. The detector is configured to output one of a first control word and a second control word that is derived from the first control word as the oscillator tuning word.
Abstract translation: 本文公开了一种电路和方法。 电路包括数字控制振荡器和检测器。 数字控制振荡器被配置为根据振荡器调谐字产生振荡器信号。 检测器被配置为输出从第一控制字导出的第一控制字和第二控制字中的一个作为振荡器调谐字。
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Patent Agency Ranking
6.发明申请THREE DIMENSIONAL CIRCUIT INCLUDING SHIELDED INDUCTOR AND METHOD OF FORMING SAME 审中-公开包括屏蔽电感器的三维电路及其形成方法公开(公告)号：US20150249051A1
公开(公告)日：2015-09-03
申请号：US14712940
申请日：2015-05-15
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor： Ming Hsien TSAI , Hsieh-Hung HSIEH , Tzu-Jin YEH , Chewn-Pu JOU , Sa-Lly LIU , Fu-Lung HSUEH
CPC classification number: H01L23/5226 , H01L23/481 , H01L23/5225 , H01L23/5227 , H01L23/5384 , H01L23/585 , H01L23/645 , H01L25/0657 , H01L27/0688 , H01L27/0705 , H01L27/092 , H01L28/10 , H01L2225/06527 , H01L2225/06537 , H01L2225/06544 , H01L2924/0002 , H03F1/26 , H03F3/04 , H03F2200/294 , H03F2200/372 , H01L2924/00
Abstract: The three dimensional (3D) circuit includes a first tier including a semiconductor substrate, a second tier disposed adjacent to the first tier, a three dimensional inductor including an inductive element portion, the inductive element portion including a conductive via extending from the first tier to a dielectric layer of the second tier. The 3D circuit includes a ground shield surrounding at least a portion of the conductive via. In some embodiments, the ground shield includes a hollow cylindrical cage. In some embodiments, the 3D circuit is a low noise amplifier.
Abstract translation: 三维（3D）电路包括包括半导体衬底的第一层，与第一层相邻设置的第二层，包括电感元件部分的三维电感器，电感元件部分包括从第一层延伸到 第二层的介电层。 3D电路包括围绕导电通孔的至少一部分的接地屏蔽。 在一些实施例中，接地屏蔽包括中空圆柱形笼。 在一些实施例中，3D电路是低噪声放大器。
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公开(公告)号：US20150116018A1
公开(公告)日：2015-04-30
申请号：US14320168
申请日：2014-06-30
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor： Huan-Neng CHEN , Kuang-Kai YEN , Feng-Wei KUO , Hsien-Yuan LIAO , Tsung-Hsiung LEE , Chewn-Pu JOU , Robert Bogdan STASZEWSKI
CPC classification number: H03L7/091 , H03L7/085 , H03L7/093 , H03L7/0991 , H03L2207/50
Abstract: A phase-locked loop circuit, a phase converter module thereof and a phase-locked controlling method are disclosed herein. The phase converter module is suitable for a phase-locked loop circuit including a digitally-controlled oscillator (DCO) for generating an oscillator output signal and a divider for converting the oscillator output signal into N-phased oscillator output signals. The phase converter module includes a period extender, a phase finder and a time-to-digital converter. The period extender is configured for extending the N-phased oscillator output signals into M*N-phased oscillator output signals corresponding to M oscillation period of the digitally-controlled oscillator. The phase finder is configured for sampling the oscillator output signal with the M*N-phased oscillator output signals to calculate an estimated value of the fractional phase part. The time-to-digital converter is configured to calculate a precise value of the fractional phase part within one sub-period.
Abstract translation: 本文公开了一种锁相环电路，其相变转换器模块和锁相控制方法。 相位转换器模块适用于包括用于产生振荡器输出信号的数字控制振荡器（DCO）和用于将振荡器输出信号转换成N相振荡器输出信号的分频器的锁相环电路。 相位转换器模块包括周期延长器，相位取样器和时间 - 数字转换器。 周期延长器被配置为将N相振荡器输出信号扩展到对应于数字控制振荡器的M个振荡周期的M * N个相位振荡器输出信号。 相位器被配置为用M * N相位振荡器输出信号对振荡器输出信号进行采样，以计算分数阶段的估计值。 时间 - 数字转换器被配置为计算一个子周期内的分数阶段的精确值。
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公开(公告)号：US20250060645A1
公开(公告)日：2025-02-20
申请号：US18936859
申请日：2024-11-04
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Lan-Chou CHO , Chewn-Pu JOU , Min-Hsiang HSU
Abstract: Apparatus, circuits and methods for reducing mismatch in an electro-optic modulator are described herein. In some embodiments, a described optical includes: a splitter configured for splitting an input optical signal into a first optical signal and a second optical signal; a phase shifter coupled to the splitter; and a combiner coupled to the phase shifter. The phase shifter includes: a first waveguide arm configured for controlling a first phase of the first optical signal to generate a first phase-controlled optical signal, and a second waveguide arm configured for controlling a second phase of the second optical signal to generate a second phase-controlled optical signal. Each of the first and second waveguide arms includes: a plurality of straight segments and a plurality of curved segments. The combiner is configured for combining the first and second phase-controlled optical signals to generate an output optical signal.
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公开(公告)号：US20240160080A1
公开(公告)日：2024-05-16
申请号：US18424609
申请日：2024-01-26
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Huan-Neng CHEN , Chewn-Pu JOU , Lan-Chou CHO , Feng-Wei KUO
CPC classification number: G02F1/2257 , G02F1/01708 , G02F1/025 , G02F1/212 , G02F2203/50
Abstract: In an embodiment, a phase shifter includes: a light input end; a light output end; a p-type semiconductor material, and an n-type semiconductor material contacting the p-type semiconductor material along a boundary area, wherein the boundary area is greater than a length from the light input end to the light output end multiplied by a core width of the phase shifter.
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公开(公告)号：US20230354503A1
公开(公告)日：2023-11-02
申请号：US18344652
申请日：2023-06-29
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor： Jiun-Yi WU , Chien-Hsun LEE , Chewn-Pu JOU , Fu-Lung HSUEH
IPC: H05K1/02 , H01L21/768 , H01L21/48 , H01L23/498 , H01L23/552 , H05K1/11 , H05K3/00 , H05K3/40 , H05K3/42
CPC classification number: H05K1/0216 , H05K1/024 , H01L21/76805 , H05K1/0222 , H01L21/485 , H01L21/486 , H01L23/49827 , H01L23/552 , H05K1/113 , H05K1/115 , H05K3/0047 , H05K3/4007 , H05K3/423 , H05K1/0245 , H05K3/42 , H05K2201/0959 , Y10T29/49165 , H05K3/4038 , H05K2201/0723 , H05K2201/09545 , H05K2201/09645
Abstract: An interconnect structure includes a dielectric block, a first conductive plug, a second conductive plug, a substrate, a first conductive line, and a second conductive line. The first conductive plug and the second conductive plug are surrounded by the dielectric block. The substrate surrounds the dielectric block. The first conductive line is connected to the first conductive plug and is in contact with a top surface of the dielectric block. The second conductive line is connected to the second conductive plug.
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