公开(公告)号：US12237159B2

公开(公告)日：2025-02-25

申请号：US18472556

申请日：2023-09-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Hsi Wang ,  Yen-Yu Chen

IPC: H01J37/34 ,  C23C14/34 ,  H01L21/033

Abstract: A deposition apparatus includes a process chamber, a wafer support in the process chamber, a backplane structure having a first surface in the process chamber facing the wafer support, a target having a second surface facing the first surface and a third surface facing the wafer support, and an adhesion structure in physical contact with the backplane structure and the target. The adhesion structure has an adhesion material layer, and a spacer embedded in the adhesion material layer.

公开(公告)号：US12094927B2

公开(公告)日：2024-09-17

申请号：US17815999

申请日：2022-07-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yen-Yu Chen ,  Chung-Liang Cheng

IPC: H01L29/06 ,  H01L21/8234 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/0653 ,  H01L21/823431 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/785 ,  H01L2029/7858

Abstract: The present disclosure is directed to gate-all-around (GAA) transistor structures with a low level of leakage current and low power consumption. For example, the GAA transistor includes a semiconductor layer with a first source/drain (S/D) epitaxial structure and a second S/D epitaxial structure disposed thereon, where the first and second S/D epitaxial structures are spaced apart by semiconductor nano-sheet layers. The semiconductor structure further includes isolation structures interposed between the semiconductor layer and each of the first and second S/D epitaxial structures. The GAA transistor further includes a gate stack surrounding the semiconductor nano-sheet layers.

公开(公告)号：US12040293B2

公开(公告)日：2024-07-16

申请号：US18055241

申请日：2022-11-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih Wei Bih ,  Sheng-Wei Yeh ,  Yen-Yu Chen ,  Wen-Hao Cheng ,  Chih-Wei Lin ,  Chun-Chih Lin

IPC: H01L23/532 ,  H01L21/02 ,  H01L23/00 ,  H01L23/525

CPC classification number: H01L24/05 ,  H01L21/02068 ,  H01L24/03 ,  H01L2224/02321 ,  H01L2224/02331 ,  H01L2224/02372 ,  H01L2224/02377 ,  H01L2224/02381 ,  H01L2224/0239 ,  H01L2224/024 ,  H01L2224/0345 ,  H01L2224/035 ,  H01L2224/0391 ,  H01L2224/05008 ,  H01L2224/05083 ,  H01L2224/05181 ,  H01L2224/05187 ,  H01L2224/05188 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2924/04953 ,  H01L2924/0535 ,  H01L2924/05994

Abstract: The present disclosure provides an integrated circuit (IC) structure. The IC structure includes a semiconductor substrate; an interconnection structure formed on the semiconductor substrate; and a redistribution layer (RDL) metallic feature formed on the interconnection structure. The RDL metallic feature further includes a barrier layer disposed on the interconnection structure; a diffusion layer disposed on the barrier layer, wherein the diffusion layer includes metal and oxygen; and a metallic layer disposed on the diffusion layer.

公开(公告)号：US11948800B2

公开(公告)日：2024-04-02

申请号：US18066203

申请日：2022-12-14

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yen-Yu Chen ,  Yu-Chi Lu ,  Chih-Pin Tsao ,  Shih-Hsun Chang

IPC: H01L21/28 ,  H01L29/49

CPC classification number: H01L21/28088 ,  H01L21/28185 ,  H01L29/4966

Abstract: A device includes a pair of gate spacers on a substrate, and a gate structure on the substrate and between the gate spacers. The gate structure includes an interfacial layer, a metal oxide layer, a nitride-containing layer, a tungsten-containing layer, and a metal compound layer. The interfacial layer is over the substrate. The metal oxide layer is over the interfacial layer. The nitride-containing layer is over the metal oxide layer. The tungsten-containing layer is over the nitride-containing layer. The metal compound layer is over the tungsten-containing layer. The metal compound layer has a different material than a material of the tungsten-containing layer.

公开(公告)号：US20230386917A1

公开(公告)日：2023-11-30

申请号：US18362676

申请日：2023-07-31

Applicant: Taiwan Semiconductor Manufacturing Co, Ltd.

Inventor： Yen-Yu Chen ,  Chung-Liang Cheng

IPC: H01L21/768 ,  H01L21/225 ,  H01L29/40 ,  H01L29/417

CPC classification number: H01L21/76879 ,  H01L21/76882 ,  H01L21/76876 ,  H01L21/76843 ,  H01L21/2254 ,  H01L21/76856 ,  H01L29/401 ,  H01L29/41791 ,  H01L21/76865 ,  H01L29/456

Abstract: A method includes etching a dielectric layer to form a trench in the dielectric layer, depositing a metal layer extending into the trench, performing a nitridation process on the metal layer to convert a portion of the metal layer into a metal nitride layer, performing an oxidation process on the metal nitride layer to form a metal oxynitride layer, removing the metal oxynitride layer, and filling a metallic material into the trench using a bottom-up deposition process to form a contact plug.

公开(公告)号：US11784046B2

公开(公告)日：2023-10-10

申请号：US17150356

申请日：2021-01-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jia-Lin Wei ,  Ming-Hui Weng ,  Chih-Cheng Liu ,  Yi-Chen Kuo ,  Yen-Yu Chen ,  Yahru Cheng ,  Jr-Hung Li ,  Ching-Yu Chang ,  Tze-Liang Lee ,  Chi-Ming Yang

IPC: H01L21/033 ,  H01L21/308 ,  G03F7/20 ,  G03F1/22 ,  G03F7/00

CPC classification number: H01L21/0332 ,  G03F1/22 ,  G03F7/70033 ,  H01L21/0334 ,  H01L21/3081

Abstract: A method of manufacturing semiconductor device includes forming a multilayer photoresist structure including a metal-containing photoresist over a substrate. The multilayer photoresist structure includes two or more metal-containing photoresist layers having different physical parameters. The metal-containing photoresist is a reaction product of a first precursor and a second precursor, and each layer of the multilayer photoresist structure is formed using different photoresist layer formation parameters. The different photoresist layer formation parameters are one or more selected from the group consisting of the first precursor, an amount of the first precursor, the second precursor, an amount of the second precursor, a length of time each photoresist layer formation operation, and heating conditions of the photoresist layers. The multilayer photoresist structure is selectively exposed to actinic radiation to form a latent pattern, and the latent pattern is developed by applying developer to the selectively exposed multilayer photoresist structure to form the pattern.

公开(公告)号：US11728226B2

公开(公告)日：2023-08-15

申请号：US16994267

申请日：2020-08-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wen-Hao Cheng ,  Hsuan-Chih Chu ,  Yen-Yu Chen ,  Yi-Ming Dai

IPC: H01L21/66 ,  C23C14/35 ,  C23C14/54 ,  H01J37/32 ,  H01J37/34

CPC classification number: H01L22/26 ,  C23C14/351 ,  C23C14/545 ,  H01J37/32715 ,  H01J37/3455 ,  H01J37/3458

Abstract: A deposition system provides a feature that may reduce costs of the sputtering process by increasing a target change interval. The deposition system provides an array of magnet members which generate a magnetic field and redirect the magnetic field based on target thickness measurement data. To adjust or redirect the magnetic field, at least one of the magnet members in the array tilts to focus on an area of the target where more target material remains than other areas. As a result, more ion, e.g., argon ion bombardment occurs on the area, creating more uniform erosion on the target surface.

公开(公告)号：US11631640B2

公开(公告)日：2023-04-18

申请号：US17675302

申请日：2022-02-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yen-Yu Chen ,  Chung-Liang Cheng

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/535 ,  H01L21/02 ,  H01L23/532

Abstract: The present disclosure describes a method for forming a barrier structure between liner-free conductive structures and underlying conductive structures. The method includes forming openings in a dielectric layer disposed on a contact layer, where the openings expose conductive structures in the contact layer. A first metal layer is deposited in the openings and is grown thicker on top surfaces of the conductive structures and thinner on sidewall surfaces of the openings. The method further includes exposing the first metal layer to ammonia to form a bilayer with the first metal layer and a nitride of the first metal layer, and subsequently exposing the nitride to an oxygen plasma to convert a portion of the nitride of the first metal layer to an oxide layer. The method also includes removing the oxide layer and forming a semiconductor-containing layer on the nitride of the first metal layer.

公开(公告)号：US20210242092A1

公开(公告)日：2021-08-05

申请号：US16925893

申请日：2020-07-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yen-Yu Chen ,  Chung-Liang Cheng

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/49 ,  H01L21/033 ,  H01L29/06 ,  H01L29/78

Abstract: A semiconductor device includes a first gate structure that includes a first interfacial layer, a first gate dielectric layer disposed over the first interfacial layer, and a first gate electrode disposed over the first gate dielectric layer. The semiconductor device also includes a second gate structure that includes a second interfacial layer, a second gate dielectric layer disposed over the second interfacial layer, and a second gate electrode disposed over the second gate dielectric layer. The first interfacial layer contains a different amount of a dipole material than the second interfacial layer.

公开(公告)号：US20210115554A1

公开(公告)日：2021-04-22

申请号：US16657832

申请日：2019-10-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wen-Hao Cheng ,  Yen-Yu Chen ,  Yi-Ming Dai

IPC: C23C16/02 ,  C23C16/458 ,  C23C16/34 ,  C23C14/02 ,  C23C16/46 ,  C23C14/34

Abstract: The present disclosure provides a multifunction chamber having a multifunctional shutter disk. The shutter disk includes a lamp device, a DC/RF power device, and a gas line on one surface of the shutter disk. With this configuration, simplifying the chamber type is possible as the various specific, dedicated chambers such as a degas chamber, a pre-clean chamber, a CVD/PVD chamber are not required. By using the multifunctional shutter disk, the degassing function and the pre-cleaning function are provided within a single chamber. Accordingly, a separate degas chamber and a pre-clean chamber are no longer required and the overall transfer time between chambers is reduced or eliminated.