公开(公告)号：US09263257B2

公开(公告)日：2016-02-16

申请号：US14312707

申请日：2014-06-24

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chin-Cheng Chien ,  Hsin-Kuo Hsu ,  Chih-Chien Liu ,  Chin-Fu Lin ,  Chun-Yuan Wu

IPC: H01L21/205 ,  H01L21/336 ,  H01L21/8232 ,  H01L29/08 ,  H01L29/16 ,  H01L29/43 ,  H01L29/78 ,  H01L29/417 ,  H01L21/02 ,  H01L21/311 ,  H01L29/36 ,  H01L29/06

CPC classification number: H01L29/66795 ,  H01L21/0228 ,  H01L21/02532 ,  H01L21/30604 ,  H01L21/31111 ,  H01L29/06 ,  H01L29/0657 ,  H01L29/1054 ,  H01L29/36 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7853

Abstract: A semiconductor device with fin-shaped structure is disclosed. The semiconductor device includes: a substrate; a fin-shaped structure on the substrate; and an epitaxial layer on a top surface and part of the sidewall of the fin-shaped structure, in which the epitaxial layer and the fin-shaped structure includes a linear gradient of germanium concentration therebetween.

Abstract translation: 公开了一种具有鳍状结构的半导体器件。 半导体器件包括：衬底; 基板上的鳍状结构; 以及在鳍状结构的顶表面和侧壁的一部分上的外延层，其中外延层和鳍状结构在其间包括锗浓度的线性梯度。

公开(公告)号：US20140295629A1

公开(公告)日：2014-10-02

申请号：US13850887

申请日：2013-03-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Tsai-Yu Wen ,  Tsuo-Wen Lu ,  Yu-Ren Wang ,  Chin-Cheng Chien ,  Tien-Wei Yu ,  Hsin-Kuo Hsu ,  Yu-Shu Lin ,  Szu-Hao Lai ,  Ming-Hua Chang

IPC: H01L21/8238

CPC classification number: H01L21/823814 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823807 ,  Y10S438/938

Abstract: A method of forming a semiconductor device is disclosed. At least one gate structure is provided on a substrate, wherein the gate structure includes a first spacer formed on a sidewall of a gate. A first disposable spacer material layer is deposited on the substrate covering the gate structure. The first disposable spacer material layer is etched to form a first disposable spacer on the first spacer. A second disposable spacer material layer is deposited on the substrate covering the gate structure. The second disposable spacer material layer is etched to form a second disposable spacer on the first disposable spacer. A portion of the substrate is removed, by using the first and second disposable spacers as a mask, so as to form two recesses in the substrate beside the gate structure. A stress-inducing layer is formed in the recesses.

Abstract translation: 公开了一种形成半导体器件的方法。 至少一个栅极结构设置在衬底上，其中栅极结构包括形成在栅极的侧壁上的第一间隔物。 在覆盖栅极结构的衬底上沉积第一一次性间隔物层。 第一一次性间隔物材料层被蚀刻以在第一间隔物上形成第一一次性间隔物。 在覆盖栅极结构的衬底上沉积第二一次性间隔物材料层。 蚀刻第二一次性间隔材料层以在第一一次性间隔件上形成第二一次性间隔件。 通过使用第一和第二一次性间隔件作为掩模来去除衬底的一部分，以在栅极结构旁边的衬底中形成两个凹部。 在凹部中形成应力诱导层。

公开(公告)号：US20210273076A1

公开(公告)日：2021-09-02

申请号：US16802564

申请日：2020-02-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yang-Ju Lu ,  Chun-Yi Wang ,  Fu-Shou Tsai ,  Yong-Yi Lin ,  Ching-Yang Chuang ,  Wen-Chin Lin ,  Hsin-Kuo Hsu

IPC: H01L29/66 ,  H01L21/3105 ,  H01L21/02

Abstract: A method of forming a gate includes the following steps. A gate structure is formed on a substrate. An etch stop layer is formed on the gate structure and the substrate. A dielectric layer is formed to cover the etch stop layer. The dielectric layer is planarized to form a planarized top surface of the dielectric layer and expose a portion of the etch stop layer on the gate structure. An oxygen containing treatment is performed to form an oxygen containing layer on the exposed etch stop layer. A deposition process is performed to form an oxide layer covering the planarized top surface of the dielectric layer and the oxygen containing layer.

公开(公告)号：US20250169368A1

公开(公告)日：2025-05-22

申请号：US18407360

申请日：2024-01-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chau-Chung Hou ,  Kun-Ju Li ,  Hsin-Jung Liu ,  Ching-Hua Hsu ,  Chen-Yi Weng ,  Chih-Yueh Li ,  Hsin-Kuo Hsu ,  Ying-Chu Chen ,  Yi-Chen Hsiao

IPC: H10N50/01 ,  G11C11/16 ,  H10B61/00 ,  H10N50/80

Abstract: A method of forming a semiconductor structure is disclosed. A substrate is provided having a memory array area and a peripheral region. A memory structure is formed on the substrate in the memory array area. A step height is formed between the memory array area and the peripheral region. A dielectric layer is deposited. The dielectric layer covers the memory structure. A reverse etching process is performed to remove part of the dielectric layer from the memory array area, thereby forming an upwardly protruding wall structure along the perimeter of the memory array area, wherein the thickness of the dielectric layer in the memory array area increases from the central area of the memory array area to the periphery of the memory array area. A polishing process is performed on the dielectric layer to remove the upwardly protruding wall structure from the memory array area.

公开(公告)号：US09461150B2

公开(公告)日：2016-10-04

申请号：US14979594

申请日：2015-12-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chin-Cheng Chien ,  Hsin-Kuo Hsu ,  Chih-Chien Liu ,  Chin-Fu Lin ,  Chun-Yuan Wu

IPC: H01L29/66 ,  H01L21/02 ,  H01L29/10 ,  H01L29/78 ,  H01L29/06 ,  H01L21/311 ,  H01L29/36

CPC classification number: H01L29/66795 ,  H01L21/0228 ,  H01L21/02532 ,  H01L21/30604 ,  H01L21/31111 ,  H01L29/06 ,  H01L29/0657 ,  H01L29/1054 ,  H01L29/36 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7853

Abstract: A method for fabricating semiconductor device with fin-shaped structure is disclosed. The method includes the steps of: forming a fin-shaped structure on a substrate; forming a first dielectric layer on the substrate and the fin-shaped structure; depositing a second dielectric layer on the first dielectric layer; etching back a portion of the second dielectric layer; removing part of the first dielectric layer to expose a top surface and part of the sidewall of the fin-shaped structure; forming an epitaxial layer to cover the exposed top surface and part of the sidewall of the fin-shaped structure; and removing a portion of the second dielectric layer.

Abstract translation: 公开了一种制造具有鳍状结构的半导体器件的方法。 该方法包括以下步骤：在衬底上形成鳍状结构; 在所述基板上形成第一电介质层和所述鳍状结构; 在所述第一电介质层上沉积第二电介质层; 蚀刻第二介电层的一部分; 去除所述第一电介质层的一部分以暴露所述鳍状结构的顶表面和所述侧壁的一部分; 形成外延层以覆盖所述鳍状结构的暴露的顶表面和所述侧壁的一部分; 以及去除所述第二电介质层的一部分。

公开(公告)号：US09230912B2

公开(公告)日：2016-01-05

申请号：US14279602

申请日：2014-05-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hsin-Kuo Hsu ,  Li-Chieh Hsu ,  Hsiang-Hao Chen ,  Chung-Wei Hsueh

IPC: H01L21/311 ,  H01L23/528 ,  H01L23/532 ,  H01L21/768 ,  H01L21/3213 ,  H01L21/321

CPC classification number: H01L23/528 ,  H01L21/3212 ,  H01L21/32134 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/7685 ,  H01L21/76877 ,  H01L21/76883 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for manufacturing a semiconductor device and a device manufactured using the same are provided. According to the embodiment, substrate with a dielectric layer formed thereon is provided. Plural trenches are defined in the dielectric layer, and the trenches are isolated by the dielectric layer. A first barrier layer is formed in the trenches as barrier liners of the trenches, followed by filling the trenches with a conductor. Then, the conductor in the trenches is partially removed to form a plurality of recesses, wherein remained conductor has a flat surface. Next, a second barrier layer is formed in the recesses as barrier caps of the trenches.

Abstract translation: 提供一种制造半导体器件的方法和使用其制造的器件。 根据本实施例，提供了形成有电介质层的基板。 在电介质层中限定多个沟槽，并且通过电介质层隔离沟槽。 在沟槽中形成第一阻挡层作为沟槽的阻挡层，然后用导体填充沟槽。 然后，沟槽中的导体被部分地去除以形成多个凹槽，其中保留的导体具有平坦的表面。 接下来，在凹槽中形成第二阻挡层作为沟槽的阻挡盖。

公开(公告)号：US09034705B2

公开(公告)日：2015-05-19

申请号：US13850887

申请日：2013-03-26

Applicant: United Microelectronics Corp.

Inventor： Tsai-Yu Wen ,  Tsuo-Wen Lu ,  Yu-Ren Wang ,  Chin-Cheng Chien ,  Tien-Wei Yu ,  Hsin-Kuo Hsu ,  Yu-Shu Lin ,  Szu-Hao Lai ,  Ming-Hua Chang

IPC: H01L21/8238 ,  H01L21/8234

CPC classification number: H01L21/823814 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823807 ,  Y10S438/938

Abstract: A method of forming a semiconductor device is disclosed. At least one gate structure is provided on a substrate, wherein the gate structure includes a first spacer formed on a sidewall of a gate. A first disposable spacer material layer is deposited on the substrate covering the gate structure. The first disposable spacer material layer is etched to form a first disposable spacer on the first spacer. A second disposable spacer material layer is deposited on the substrate covering the gate structure. The second disposable spacer material layer is etched to form a second disposable spacer on the first disposable spacer. A portion of the substrate is removed, by using the first and second disposable spacers as a mask, so as to form two recesses in the substrate beside the gate structure. A stress-inducing layer is formed in the recesses.

Abstract translation: 公开了一种形成半导体器件的方法。 至少一个栅极结构设置在衬底上，其中栅极结构包括形成在栅极的侧壁上的第一间隔物。 在覆盖栅极结构的衬底上沉积第一一次性间隔物层。 第一一次性间隔物材料层被蚀刻以在第一间隔物上形成第一一次性间隔物。 在覆盖栅极结构的衬底上沉积第二一次性间隔物材料层。 蚀刻第二一次性间隔材料层以在第一一次性间隔件上形成第二一次性间隔件。 通过使用第一和第二一次性间隔件作为掩模来去除衬底的一部分，以在栅极结构旁边的衬底中形成两个凹部。 在凹部中形成应力诱导层。

公开(公告)号：US08853060B1

公开(公告)日：2014-10-07

申请号：US13902862

申请日：2013-05-27

Applicant: United Microelectronics Corp.

Inventor： Szu-Hao Lai ,  Chun-Yuan Wu ,  Chin-Cheng Chien ,  Tien-Wei Yu ,  Ming-Hua Chang ,  Yu-Shu Lin ,  Tsai-Yu Wen ,  Hsin-Kuo Hsu

IPC: H01L21/20 ,  H01L21/02

CPC classification number: H01L21/02532 ,  H01L21/0237 ,  H01L21/0245 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/02639 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/7848

Abstract: An epitaxial process includes the following step. A recess is formed in a substrate. A seeding layer is formed to cover a surface of the recess. A buffer layer is formed on the seeding layer. An etching process is performed on the buffer layer to homogenize and shape the buffer layer. An epitaxial layer is formed on the homogenized flat bottom shape buffer layer.

Abstract translation: 外延工艺包括以下步骤。 在基板上形成凹部。 形成接合层以覆盖凹部的表面。 在接种层上形成缓冲层。 对缓冲层进行蚀刻处理，使缓冲层均匀化并形成。 在均质化的平底形状缓冲层上形成外延层。

公开(公告)号：US10381228B2

公开(公告)日：2019-08-13

申请号：US14631807

申请日：2015-02-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Ying Lin ,  Ted Ming-Lang Guo ,  Chin-Cheng Chien ,  Chih-Chien Liu ,  Hsin-Kuo Hsu ,  Chin-Fu Lin ,  Chun-Yuan Wu

IPC: H01L21/306 ,  H01L21/3065 ,  H01L29/08 ,  H01L29/66 ,  H01L29/78

Abstract: An epitaxial process applying light illumination includes the following steps. A substrate is provided. A dry etching process and a wet etching process are performed to form a recess in the substrate, wherein an infrared light illuminates while the wet etching process is performed. An epitaxial structure is formed in the recess.

公开(公告)号：US20160211144A1

公开(公告)日：2016-07-21

申请号：US14631807

申请日：2015-02-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Ying Lin ,  Ted Ming-Lang Guo ,  Chin-Cheng Chien ,  Chih-Chien Liu ,  Hsin-Kuo Hsu ,  Chin-Fu Lin ,  Chun-Yuan Wu

IPC: H01L21/306 ,  H01L29/66 ,  H01L29/08 ,  H01L21/3065

CPC classification number: H01L21/30608 ,  H01L21/3065 ,  H01L29/0847 ,  H01L29/66795 ,  H01L29/785

Abstract: An epitaxial process applying light illumination includes the following steps. A substrate is provided. A dry etching process and a wet etching process are performed to form a recess in the substrate, wherein an infrared light illuminates while the wet etching process is performed. An epitaxial structure is formed in the recess.

Abstract translation: 施加光照射的外延工艺包括以下步骤。 提供基板。 执行干蚀刻工艺和湿蚀刻工艺以在衬底中形成凹部，其中在执行湿蚀刻工艺时红外光照亮。 在凹部中形成外延结构。