公开(公告)号：US09966434B2

公开(公告)日：2018-05-08

申请号：US15632399

申请日：2017-06-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ming-Shiou Hsieh ,  Chun-Yao Yang ,  Shi-You Liu ,  Rong-Sin Lin ,  Han-Ting Yen ,  Yi-Wei Chen ,  I-Cheng Hu ,  Yu-Shu Lin ,  Neng-Hui Yang

IPC: H01L29/08 ,  H01L21/02 ,  H01L29/165 ,  H01L29/36 ,  H01L21/265 ,  H01L21/324 ,  H01L29/167 ,  H01L21/283 ,  H01L21/768 ,  H01L21/8234 ,  H01L29/417 ,  H01L29/78 ,  H01L29/06 ,  H01L27/088

CPC classification number: H01L29/0847 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/2257 ,  H01L21/265 ,  H01L21/26513 ,  H01L21/283 ,  H01L21/324 ,  H01L21/76877 ,  H01L21/76897 ,  H01L21/823425 ,  H01L21/823475 ,  H01L23/485 ,  H01L23/528 ,  H01L23/53252 ,  H01L27/088 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/161 ,  H01L29/165 ,  H01L29/167 ,  H01L29/36 ,  H01L29/41783 ,  H01L29/665 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

Abstract: A semiconductor device includes a substrate including a plurality of transistor devices formed thereon, at least an epitaxial structure formed in between the transistor devices, and a tri-layered structure formed on the epitaxial structure. The epitaxial structure includes a first semiconductor material and a second semiconductor material, and a lattice constant of the second semiconductor material is larger than a lattice constant of the first semiconductor material. The tri-layered structure includes an undoped epitaxial layer, a metal-semiconductor compound layer, and a doped epitaxial layer sandwiched in between the undoped epitaxial layer and the metal-semiconductor compound layer. The undoped epitaxial layer and the doped epitaxial layer include at least the second semiconductor material.

公开(公告)号：US09748147B1

公开(公告)日：2017-08-29

申请号：US15214467

申请日：2016-07-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yi-Fan Li ,  Li-Wei Feng ,  Li-Chieh Hsu ,  Chun-Jen Chen ,  I-Cheng Hu ,  Tien-I Wu ,  Yu-Shu Lin ,  Neng-Hui Yang

IPC: H01L21/20 ,  H01L21/8238 ,  H01L21/265 ,  H01L21/02 ,  H01L21/308

CPC classification number: H01L21/823821 ,  H01L21/0243 ,  H01L21/0245 ,  H01L21/02521 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02587 ,  H01L21/0262 ,  H01L21/02634 ,  H01L21/02636 ,  H01L21/02639 ,  H01L21/02661 ,  H01L21/2652 ,  H01L21/3086 ,  H01L21/823807 ,  H01L21/8258

Abstract: A method of fabricating an epitaxial layer includes providing a silicon substrate. A dielectric layer covers the silicon substrate. A recess is formed in the silicon substrate and the dielectric layer. A selective epitaxial growth process and a non-selective epitaxial growth process are performed in sequence to respectively form a first epitaxial layer and a second epitaxial layer. The first epitaxial layer does not cover the top surface of the dielectric layer. The recess is filled by the first epitaxial layer and the second epitaxial layer. Finally, the first epitaxial layer and the second epitaxial layer are planarized.

公开(公告)号：US09673324B1

公开(公告)日：2017-06-06

申请号：US15246522

申请日：2016-08-24

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Tien-I Wu ,  I-Cheng Hu ,  Yu-Shu Lin ,  Shu-Yen Chan ,  Neng-Hui Yang

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/7846 ,  H01L29/66553 ,  H01L29/66795 ,  H01L29/7842 ,  H01L29/7848 ,  H01L29/7849 ,  H01L29/785 ,  H01L29/7853

Abstract: The present invention provides a metal oxide semiconductor (MOS) device, including a substrate, a gate structure on the substrate and a source/drain region disposed in the substrate at one side of the gate structure and in at least a part of an epitaxial structure, wherein the epitaxial structure includes a first buffer layer, which is an un-doped buffer layer, including a bottom portion disposed on a bottom surface of the epitaxial structure and a sidewall portion disposed on a concave sidewall of the epitaxial structure, an epitaxial layer which is encompassed by the first buffer layer, and a semiconductor layer which is disposed between the first buffer layer and the epitaxial layer. The source/drain region is disposed in the epitaxial structure.

公开(公告)号：US20170330937A1

公开(公告)日：2017-11-16

申请号：US15632399

申请日：2017-06-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ming-Shiou Hsieh ,  Chun-Yao Yang ,  Shi-You Liu ,  Rong-Sin Lin ,  Han-Ting Yen ,  Yi-Wei Chen ,  I-Cheng Hu ,  Yu-Shu Lin ,  Neng-Hui Yang

IPC: H01L29/08 ,  H01L29/417 ,  H01L29/36 ,  H01L29/167 ,  H01L29/165 ,  H01L21/265 ,  H01L21/02 ,  H01L21/8234 ,  H01L21/768 ,  H01L21/324 ,  H01L21/283 ,  H01L29/78 ,  H01L29/06 ,  H01L27/088

CPC classification number: H01L29/0847 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/2257 ,  H01L21/265 ,  H01L21/26513 ,  H01L21/283 ,  H01L21/324 ,  H01L21/76877 ,  H01L21/76897 ,  H01L21/823425 ,  H01L21/823475 ,  H01L23/485 ,  H01L23/528 ,  H01L23/53252 ,  H01L27/088 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/161 ,  H01L29/165 ,  H01L29/167 ,  H01L29/36 ,  H01L29/41783 ,  H01L29/665 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

Abstract: A semiconductor device includes a substrate including a plurality of transistor devices formed thereon, at least an epitaxial structure formed in between the transistor devices, and a tri-layered structure formed on the epitaxial structure. The epitaxial structure includes a first semiconductor material and a second semiconductor material, and a lattice constant of the second semiconductor material is larger than a lattice constant of the first semiconductor material. The tri-layered structure includes an undoped epitaxial layer, a metal-semiconductor compound layer, and a doped epitaxial layer sandwiched in between the undoped epitaxial layer and the metal-semiconductor compound layer. The undoped epitaxial layer and the doped epitaxial layer include at least the second semiconductor material.

公开(公告)号：US20170294540A1

公开(公告)日：2017-10-12

申请号：US15095484

申请日：2016-04-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： I-Cheng Hu ,  Kai-Hsiang Wang ,  Tien-I Wu ,  Yu-Shu Lin ,  Shu-Yen Chan

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/40 ,  H01L29/49 ,  H01L29/161 ,  H01L29/66 ,  H01L29/45

CPC classification number: H01L29/7848 ,  H01L21/823418 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7843

Abstract: A semiconductor structure and a method for manufacturing the same are provided. The semiconductor includes a substrate, two source/drain regions, a gate structure and two salicide layers. The two source/drain regions are partially disposed in the substrate each with a substantially flat top surface higher than a top surface of the substrate, and the two source/drain regions are separated from each other. The two source/drain regions are formed of an epitaxial material. The gate structure is disposed on the substrate between the two source/drain regions. The two salicide layers are disposed on the substantially flat top surfaces of the two source/drain regions, respectively.

公开(公告)号：US09214551B2

公开(公告)日：2015-12-15

申请号：US14183545

申请日：2014-02-19

Applicant: United Microelectronics Corp.

Inventor： Ming-Hua Chang ,  Tien-Wei Yu ,  I-Cheng Hu ,  Chieh-Lung Wu ,  Yu-Shu Lin ,  Chun-Jen Chen ,  Tsung-Mu Yang ,  Tien-Chen Chan ,  Chin-Cheng Chien

IPC: H01L29/161 ,  H01L29/165 ,  H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L21/306

CPC classification number: H01L29/7848 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/30604 ,  H01L29/045 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66477 ,  H01L29/66636 ,  H01L29/7834

Abstract: A method for fabricating a semiconductor device, and a semiconductor device made with the method are described. In the method, a cavity is formed in a substrate, a first epitaxy process is performed under a pressure higher than 65 torr to form a buffer layer in the cavity, and a second epitaxy process is performed to form a semiconductor compound layer on the buffer layer in the cavity. In the semiconductor device, the ratio (S/Y) of the thickness S of the buffer layer on a lower sidewall of the cavity to the thickness Y of the buffer layer at the bottom of the cavity ranges from 0.6 to 0.8.

Abstract translation: 描述了一种用于制造半导体器件的方法，以及用该方法制造的半导体器件。 在该方法中，在衬底中形成腔体，在高于65托的压力下进行第一外延工艺，以在空腔中形成缓冲层，并且进行第二外延工艺以在缓冲器上形成半导体化合物层 在空腔中的层。 在半导体装置中，空腔下侧的缓冲层的厚度S与空腔底部的缓冲层的厚度Y的比值（S / Y）为0.6〜0.8。

公开(公告)号：US20150236158A1

公开(公告)日：2015-08-20

申请号：US14183545

申请日：2014-02-19

Applicant: United Microelectronics Corp.

Inventor： Ming-Hua Chang ,  Tien-Wei Yu ,  I-Cheng Hu ,  Chieh-Lung Wu ,  Yu-Shu Lin ,  Chun-Jen Chen ,  Tsung-Mu Yang ,  Tien-Chen Chan ,  Chin-Cheng Chien

IPC: H01L29/78 ,  H01L21/306 ,  H01L29/66 ,  H01L21/02 ,  H01L29/161 ,  H01L29/165

CPC classification number: H01L29/7848 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/30604 ,  H01L29/045 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66477 ,  H01L29/66636 ,  H01L29/7834

Abstract: A method for fabricating a semiconductor device, and a semiconductor device made with the method are described. In the method, a cavity is formed in a substrate, a first epitaxy process is performed under a pressure higher than 65 torr to form a buffer layer in the cavity, and a second epitaxy process is performed to form a semiconductor compound layer on the buffer layer in the cavity. In the semiconductor device, the ratio (S/Y) of the thickness S of the buffer layer on a lower sidewall of the cavity to the thickness Y of the buffer layer at the bottom of the cavity ranges from 0.6 to 0.8.

Abstract translation: 描述了一种用于制造半导体器件的方法，以及用该方法制造的半导体器件。 在该方法中，在衬底中形成腔体，在高于65托的压力下进行第一外延工艺，以在空腔中形成缓冲层，并且进行第二外延工艺以在缓冲器上形成半导体化合物层 在空腔中的层。 在半导体装置中，空腔下侧的缓冲层的厚度S与空腔底部的缓冲层的厚度Y的比值（S / Y）为0.6〜0.8。

公开(公告)号：US10446447B2

公开(公告)日：2019-10-15

申请号：US16036831

申请日：2018-07-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yi-Fan Li ,  I-Cheng Hu ,  Chun-Jen Chen ,  Tien-I Wu ,  Yu-Shu Lin ,  Chun-Yuan Wu

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/10 ,  H01L21/762 ,  H01L21/308 ,  H01L21/3065 ,  H01L21/8238 ,  H01L29/78 ,  H01L21/311

Abstract: A method for fabricating semiconductor device includes the steps of: forming a fin-shaped structure on a substrate; forming a shallow trench isolation (STI) around the fin-shaped structure; forming a liner on the fin-shaped structure; and removing the liner and part of the fin-shaped structure so that a sidewall of the fin-shaped structure comprises a curve. Moreover, the method includes forming an epitaxial layer around the sidewall of the fin-shaped structure while a top surface of the fin-shaped structure is exposed.

公开(公告)号：US10128366B2

公开(公告)日：2018-11-13

申请号：US15890303

申请日：2018-02-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Ying Lin ,  Kuan Hsuan Ku ,  I-Cheng Hu ,  Chueh-Yang Liu ,  Shui-Yen Lu ,  Yu Shu Lin ,  Chun Yao Yang ,  Yu-Ren Wang ,  Neng-Hui Yang

IPC: H01L21/00 ,  H01L29/78 ,  H01L21/225 ,  H01L29/06 ,  H01L21/768 ,  H01L21/311 ,  H01L29/417 ,  H01L29/165 ,  H01L27/092

Abstract: A semiconductor device includes a semiconductor substrate, a gate structure formed over the semiconductor substrate, and an epitaxial structure formed partially within the semiconductor substrate. The gate structure includes a gate dielectric layer formed over the semiconductor substrate, a gate electrode formed over the gate dielectric layer, and a spacer formed on side surfaces of the gate dielectric layer and the gate electrode. A laterally extending portion of the epitaxial structure extends laterally at an area below a top surface of the semiconductor substrate in a direction toward an area below the gate structure. A lateral end of the laterally extending portion is below the spacer.

公开(公告)号：US20180323302A1

公开(公告)日：2018-11-08

申请号：US16036831

申请日：2018-07-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yi-Fan Li ,  I-Cheng Hu ,  Chun-Jen Chen ,  Tien-I Wu ,  Yu-Shu Lin ,  Chun-Yuan Wu

IPC: H01L29/78 ,  H01L21/762 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/088 ,  H01L21/3065 ,  H01L21/308 ,  H01L29/10

CPC classification number: H01L21/823431 ,  H01L21/3065 ,  H01L21/3085 ,  H01L21/31116 ,  H01L21/762 ,  H01L21/76205 ,  H01L21/76224 ,  H01L21/823487 ,  H01L21/823821 ,  H01L27/0886 ,  H01L29/1029 ,  H01L29/7851 ,  H01L29/7853

Abstract: A method for fabricating semiconductor device includes the steps of: forming a fin-shaped structure on a substrate; forming a shallow trench isolation (STI) around the fin-shaped structure; forming a liner on the fin-shaped structure; and removing the liner and part of the fin-shaped structure so that a sidewall of the fin-shaped structure comprises a curve. Moreover, the method includes forming an epitaxial layer around the sidewall of the fin-shaped structure while a top surface of the fin-shaped structure is exposed.