公开(公告)号：US10764996B1

公开(公告)日：2020-09-01

申请号：US16012594

申请日：2018-06-19

Applicant: Xilinx, Inc.

Inventor： Ronilo Boja ,  Inderjit Singh

IPC: H05K1/02 ,  H01L25/065 ,  H01L23/538 ,  H01L23/00 ,  H01L23/10 ,  H01L23/40

Abstract: A chip package assembly and method for fabricating the same are provided which utilize a composite stiffener selected to provide excellent resistance to warpage without detrimentally imposing excessive stress on a package substrate of the package assembly. In one example, the chip package assembly includes an integrated circuit die stacked on a top surface of a package substrate, and a composite stiffener coupled to a first edge of the package substrate. The composite stiffener includes a first stiffener member and a second stiffener member. The first stiffener member has a bottom surface bonded to the top surface of the package substrate. The second stiffener member is disposed over the first stiffener member. The second stiffener member has a bottom surface bonded to the top surface of the package substrate. The second stiffener member has a Young's modulus that is less than a Young's modulus of the first stiffener member.

公开(公告)号：US10043730B2

公开(公告)日：2018-08-07

申请号：US14867349

申请日：2015-09-28

Applicant: Xilinx, Inc.

Inventor： Gamal Refai-Ahmed ,  Tien-Yu Lee ,  Ferdinand F. Fernandez ,  Suresh Ramalingam ,  Ivor G. Barber ,  Inderjit Singh ,  Nael Zohni

IPC: H01L23/10 ,  H01L23/367 ,  H01L25/065 ,  H01L23/373 ,  H01L25/00 ,  H01L23/16 ,  H01L25/18 ,  H01L23/04 ,  H01L23/473 ,  H01L21/48 ,  H01L23/00 ,  H01L23/40

Abstract: A method and apparatus are provided which improve heat transfer between a lid and an IC die of an IC (chip) package. In one embodiment, a chip package is provided that includes a first IC die, a package substrate, a lid and a stiffener. The first IC die is coupled to the package substrate. The stiffener is coupled to the package substrate and circumscribes the first IC die. The lid has a first surface and a second surface. The second surface faces away from the first surface and towards the first IC die. The second surface of the lid is conductively coupled to the IC die, while the lid is mechanically decoupled from the stiffener.

公开(公告)号：US09865567B1

公开(公告)日：2018-01-09

申请号：US15423303

申请日：2017-02-02

Applicant: Xilinx, Inc.

Inventor： Raghunandan Chaware ,  Ganesh Hariharan ,  Inderjit Singh ,  Amitava Majumdar ,  Glenn O'Rourke

IPC: H01L21/58 ,  H01L25/065 ,  H01L25/00 ,  H01L21/82 ,  H01L21/66 ,  H01L23/00 ,  H01L21/56 ,  H01L25/16

CPC classification number: H01L25/0655 ,  H01L21/563 ,  H01L21/82 ,  H01L22/14 ,  H01L22/20 ,  H01L24/17 ,  H01L25/16 ,  H01L25/50 ,  H01L2224/17181

Abstract: An example method of manufacturing a semiconductor assembly includes: forming first integrated circuit (IC) dies and dummy dies; forming an interposer wafer including a top side having first mounting sites for the first IC dies and second mounting sites for second IC dies; attaching the first IC dies to the interposer wafer at the first mounting sites and the dummy dies to the interposer wafer at the second mounting sites; processing a backside and the top side of the interposer wafer; removing the dummy dies from the top side of the interposer wafer to expose the second mounting sites; and attaching the second IC dies to the interposer wafer at the exposed second mounting sites.

公开(公告)号：US20170092619A1

公开(公告)日：2017-03-30

申请号：US14867349

申请日：2015-09-28

Applicant: Xilinx, Inc.

Inventor： Gamal Refai-Ahmed ,  Tien-Yu Lee ,  Ferdinand F. Fernandez ,  Suresh Ramalingam ,  Ivor G. Barber ,  Inderjit Singh ,  Nael Zohni

IPC: H01L25/065 ,  H01L23/06 ,  H01L23/373 ,  H01L25/00 ,  H01L23/00 ,  H01L23/10 ,  H01L23/367

CPC classification number: H01L23/373 ,  H01L21/4882 ,  H01L23/04 ,  H01L23/16 ,  H01L23/367 ,  H01L23/40 ,  H01L23/4006 ,  H01L23/473 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L25/0655 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73203 ,  H01L2224/73253 ,  H01L2224/81815 ,  H01L2224/83385 ,  H01L2224/92125 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/3511 ,  H01L2924/35121

Abstract: A method and apparatus are provided which improve heat transfer between a lid and an IC die of an IC (chip) package. In one embodiment, a chip package is provided that includes a first IC die, a package substrate, a lid and a stiffener. The first IC die is coupled to the package substrate. The stiffener is coupled to the package substrate and circumscribes the first IC die. The lid has a first surface and a second surface. The second surface faces away from the first surface and towards the first IC die. The second surface of the lid is conductively coupled to the IC die, while the lid is mechanically decoupled from the stiffener.

公开(公告)号：US08900987B1

公开(公告)日：2014-12-02

申请号：US14046846

申请日：2013-10-04

Applicant: Xilinx, Inc.

Inventor： Inderjit Singh ,  Raghunandan Chaware ,  Ganesh Hariharan ,  Glenn O'Rourke

IPC: H01L21/44 ,  H01L23/00

CPC classification number: H01L24/11 ,  H01L21/4853 ,  H01L24/81 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/50 ,  H01L2224/0345 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05023 ,  H01L2224/05166 ,  H01L2224/05541 ,  H01L2224/05568 ,  H01L2224/05647 ,  H01L2224/11001 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/119 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/81193 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2224/81 ,  H01L2924/00014 ,  H01L2224/11 ,  H01L2924/00012 ,  H01L2924/206 ,  H01L2924/01047

Abstract: A method for removing bumps from incomplete interposer die(s) and/or defective interposer die(s) of an interposer wafer is described. The method includes forming bumps on an interposer wafer; identifying at least one incomplete interposer die and/or at least one defective interposer die of the interposer wafer; and removing bumps from the at least one incomplete interposer die and/or the at least one defective interposer die of the interposer wafer.

Abstract translation: 描述了用于从插入器晶片的不完全插入件裸片和/或插入器裸片的缺陷插入件裸片去除凸块的方法。 该方法包括在插入件晶片上形成凸块; 识别所述插入器晶片的至少一个不完全插入件裸片和/或至少一个缺陷插入器裸片; 以及从所述至少一个不完全插入器裸片和/或所述插入器晶片的所述至少一个缺陷插入器裸片去除凸块。

公开(公告)号：US11201095B1

公开(公告)日：2021-12-14

申请号：US16549801

申请日：2019-08-23

Applicant: XILINX, INC.

Inventor： Ronilo Boja ,  Inderjit Singh ,  Gerilyn Maloney ,  Chandan Bhat

IPC: H01L23/049 ,  H01L23/24 ,  H01L23/31 ,  H01L21/56

Abstract: A chip package and method for fabricating the same are provided which utilize a cover having one or more windows formed through one or more sidewalls to provide excellent resistance to warpage while allowing access to an internal volume of the chip package. In one example, the chip package includes a package substrate, an integrated circuit (IC) die, and a cover disposed over the IC die. The cover includes a lower surface facing the IC die, an upper surface facing away from the IC die, a lip extending from the lower surface, and a first sidewall extending from a first edge of the upper surface to the bottom of the lip. The lip is secured to the package substrate and encloses a volume between the lower surface and the package substrate. The IC die resides in the volume. A first elongated window is formed through the first sidewall and exposes the volume through the cover.

公开(公告)号：US09761533B2

公开(公告)日：2017-09-12

申请号：US14885757

申请日：2015-10-16

Applicant: Xilinx, Inc.

Inventor： Raghunandan Chaware ,  Amitava Majumdar ,  Glenn O'Rourke ,  Inderjit Singh

IPC: H01L23/538 ,  H01L25/18 ,  H01L25/065 ,  H01L23/00

CPC classification number: H01L23/5385 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6835 ,  H01L22/14 ,  H01L23/3114 ,  H01L23/538 ,  H01L23/5381 ,  H01L23/5384 ,  H01L23/5386 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L24/92 ,  H01L24/94 ,  H01L24/96 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/18 ,  H01L2221/68327 ,  H01L2221/68331 ,  H01L2221/68372 ,  H01L2224/03312 ,  H01L2224/0332 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/1703 ,  H01L2224/17051 ,  H01L2224/17181 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/92 ,  H01L2224/94 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/1461 ,  H01L2924/1515 ,  H01L2924/152 ,  H01L2924/153 ,  H01L2924/15311 ,  H01L2224/03 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L21/78 ,  H01L2221/68304 ,  H01L2224/81 ,  H01L21/56 ,  H01L21/304 ,  H01L2224/11 ,  H01L2221/68381 ,  H01L22/00 ,  H01L2224/1181

Abstract: Techniques for providing a semiconductor assembly having an interconnect die for die-to-die interconnection, an IC package, a method for manufacturing, and a method for routing signals in an IC package are described. In one implementation, a semiconductor assembly is provided that includes a first interconnect die coupled to a first integrated circuit (IC) die and a second IC die by inter-die connections. The first interconnect die includes solid state circuitry that provides a signal transmission path between the IC dice.

公开(公告)号：US09418909B1

公开(公告)日：2016-08-16

申请号：US14820147

申请日：2015-08-06

Applicant: Xilinx, Inc.

Inventor： Raghunandan Chaware ,  Inderjit Singh

IPC: H01L23/10 ,  H01L23/00 ,  H01L23/053 ,  H01L23/31

CPC classification number: H01L23/10 ,  H01L23/053 ,  H01L23/3142 ,  H01L23/562 ,  H01L24/26 ,  H01L24/29 ,  H01L24/32 ,  H01L24/83 ,  H01L2224/8385 ,  H01L2924/16196

Abstract: A method and apparatus are provided which improve the adhesion of a lid to an IC die of an IC (chip) package. In one embodiment, a chip package assembly is provided that includes an IC die, a package substrate and a lid. The IC die is coupled to the package substrate. The lid has a first surface and a second surface. The second surface of the lid faces away from the first surface and towards the IC die. The second surface of the lid has a plurality of engineered features. The adhesive couples the plurality of engineered features of the lid to the IC die.

Abstract translation: 提供了一种提高盖子与IC（芯片）封装的IC芯片的密合性的方法和装置。 在一个实施例中，提供了包括IC管芯，封装基板和盖子的芯片封装组件。 IC管芯耦合到封装衬底。 盖具有第一表面和第二表面。 盖的第二表面背离第一表面并朝向IC芯片。 盖的第二表面具有多个工程特征。 粘合剂将盖的多个工程特征耦合到IC管芯。

公开(公告)号：US20190267287A1

公开(公告)日：2019-08-29

申请号：US15904764

申请日：2018-02-26

Applicant: Xilinx, Inc.

Inventor： Ganesh Hariharan ,  Raghunandan Chaware ,  Inderjit Singh

IPC: H01L21/78 ,  H01L21/56 ,  H01L25/00 ,  H01L23/31

Abstract: Techniques for singulating dies from a respective workpiece and for incorporating one or more singulated die into a stacked device structure are described herein. In some examples, singulating a die from a workpiece includes chemically etching the workpiece in a scribe line. In some examples, singulating a die from a workpiece includes mechanically dicing the workpiece in a scribe line and forming a liner along a sidewall of the die. The die can be incorporated into a stacked device structure. The die can be attached to a substrate along with another die that is attached to the substrate. An encapsulant can be between each die and the substrate and laterally between the dies.

公开(公告)号：US20170110407A1

公开(公告)日：2017-04-20

申请号：US14885757

申请日：2015-10-16

Applicant: Xilinx, Inc.

Inventor： Raghunandan Chaware ,  Amitava Majumdar ,  Glenn O'Rourke ,  Inderjit Singh

IPC: H01L23/538 ,  H01L25/065 ,  H01L23/00 ,  H01L25/18

CPC classification number: H01L23/5385 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6835 ,  H01L22/14 ,  H01L23/3114 ,  H01L23/538 ,  H01L23/5381 ,  H01L23/5384 ,  H01L23/5386 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L24/92 ,  H01L24/94 ,  H01L24/96 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/18 ,  H01L2221/68327 ,  H01L2221/68331 ,  H01L2221/68372 ,  H01L2224/03312 ,  H01L2224/0332 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/1703 ,  H01L2224/17051 ,  H01L2224/17181 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/92 ,  H01L2224/94 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/1461 ,  H01L2924/1515 ,  H01L2924/152 ,  H01L2924/153 ,  H01L2924/15311 ,  H01L2224/03 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L21/78 ,  H01L2221/68304 ,  H01L2224/81 ,  H01L21/56 ,  H01L21/304 ,  H01L2224/11 ,  H01L2221/68381 ,  H01L22/00 ,  H01L2224/1181

Abstract: Techniques for providing a semiconductor assembly having an interconnect die for die-to-die interconnection, an IC package, a method for manufacturing, and a method for routing signals in an IC package are described. In one implementation, a semiconductor assembly is provided that includes a first interconnect die coupled to a first integrated circuit (IC) die and a second IC die by inter-die connections. The first interconnect die includes solid state circuitry that provides a signal transmission path between the IC dice.