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公开(公告)号：US08653639B2
公开(公告)日：2014-02-18
申请号：US13156808
申请日：2011-06-09
IPC分类号： H01L21/02
CPC分类号： H01L21/561 , H01L21/6835 , H01L22/22 , H01L23/3114 , H01L23/5389 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/24 , H01L24/25 , H01L24/27 , H01L24/29 , H01L24/32 , H01L24/75 , H01L24/81 , H01L24/82 , H01L24/83 , H01L24/92 , H01L24/94 , H01L24/95 , H01L25/0657 , H01L25/105 , H01L25/50 , H01L2221/68327 , H01L2221/6834 , H01L2224/02311 , H01L2224/02313 , H01L2224/02321 , H01L2224/0235 , H01L2224/02371 , H01L2224/02373 , H01L2224/02379 , H01L2224/0239 , H01L2224/024 , H01L2224/0345 , H01L2224/0346 , H01L2224/0401 , H01L2224/04026 , H01L2224/05008 , H01L2224/05013 , H01L2224/05147 , H01L2224/05644 , H01L2224/1146 , H01L2224/13024 , H01L2224/13144 , H01L2224/16148 , H01L2224/24011 , H01L2224/2405 , H01L2224/24146 , H01L2224/245 , H01L2224/2512 , H01L2224/25171 , H01L2224/25175 , H01L2224/25177 , H01L2224/2746 , H01L2224/29024 , H01L2224/29144 , H01L2224/32145 , H01L2224/32148 , H01L2224/75101 , H01L2224/8112 , H01L2224/81191 , H01L2224/81203 , H01L2224/81815 , H01L2224/82101 , H01L2224/82106 , H01L2224/83005 , H01L2224/8313 , H01L2224/83191 , H01L2224/83203 , H01L2224/83815 , H01L2224/8385 , H01L2224/83986 , H01L2224/92 , H01L2224/92244 , H01L2224/94 , H01L2224/95 , H01L2225/06541 , H01L2225/06551 , H01L2225/06558 , H01L2225/06565 , H01L2225/06593 , H01L2225/1058 , H01L2924/07802 , H01L2924/3511 , H01L2924/0105 , H01L2924/00014 , H01L2224/83 , H01L2224/11 , H01L2224/27 , H01L2224/82 , H01L2224/0231 , H01L21/78 , H01L2224/81 , H01L2924/00
摘要： A layered chip package includes a main body and wiring. The main body has a main part. The main part has a top surface and a bottom surface and includes a plurality of layer portions that are stacked. The wiring includes a plurality of lines passing through all the plurality of layer portions. Each layer portion includes a semiconductor chip and a plurality of electrodes. The semiconductor chip has a first surface, and a second surface opposite thereto. The plurality of electrodes are disposed on a side of the first surface of the semiconductor chip. The plurality of layer portions include two or more pairs of first and second layer portions in each of which the first and second layer portions are arranged so that the first or second surfaces of the respective semiconductor chips face each other. The plurality of electrodes include a plurality of first connection parts and a plurality of second connection parts. In the first layer portion, the plurality of first connection parts are in contact with the plurality of lines. In the second layer portion, the plurality of second connection parts are in contact with the plurality of lines.
摘要翻译： 分层芯片封装包括主体和布线。 主体有一个主要部分。 主要部分具有顶表面和底表面，并且包括堆叠的多个层部分。 布线包括穿过所有多个层部分的多条线。 各层部分包括半导体芯片和多个电极。 半导体芯片具有第一表面和与其相对的第二表面。 多个电极设置在半导体芯片的第一表面的一侧。 多个层部分包括两对或更多对第一和第二层部分，其中每个第一和第二层部分中的第一和第二层部分被布置成使得各个半导体芯片的第一或第二表面彼此面对。 多个电极包括多个第一连接部和多个第二连接部。 在第一层部分中，多个第一连接部分与多条线接触。 在第二层部分中，多个第二连接部分与多条线接触。
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公开(公告)号：US08618646B2
公开(公告)日：2013-12-31
申请号：US12902600
申请日：2010-10-12
IPC分类号： H01L23/02
CPC分类号： H01L24/92 , H01L22/22 , H01L24/03 , H01L24/05 , H01L24/13 , H01L24/16 , H01L24/96 , H01L25/0657 , H01L25/105 , H01L25/50 , H01L2224/03009 , H01L2224/0362 , H01L2224/037 , H01L2224/0401 , H01L2224/04105 , H01L2224/05008 , H01L2224/05011 , H01L2224/05012 , H01L2224/05147 , H01L2224/05569 , H01L2224/05644 , H01L2224/13144 , H01L2224/16145 , H01L2224/9202 , H01L2224/96 , H01L2225/06541 , H01L2225/06558 , H01L2225/06565 , H01L2225/1058 , H01L2924/00014 , H01L2924/07802 , H01L2924/1434 , H01L2924/181 , H01L2924/3511 , H01L2224/03 , H01L2924/0105 , H01L2924/00 , H01L2224/05552
摘要： A layered chip package includes a main body. The main body includes a main part, and further includes first terminals and second terminals disposed on the top and bottom surfaces of the main part, respectively. The main part includes first and second layer portions, and through electrodes penetrating them. The through electrodes are electrically connected to the first and second terminals. Each of the layer portions includes a semiconductor chip having a first surface and a second surface opposite thereto, and further includes surface electrodes. The surface electrodes are disposed on a side of the semiconductor chip opposite to the second surface. The first and second layer portions are bonded to each other such that the respective second surfaces face each other. The first terminals are formed by using the surface electrodes of the first layer portion. The second terminals are formed by using the surface electrodes of the second layer portion.
摘要翻译： 分层芯片封装包括主体。 主体包括主要部分，并且还包括分别设置在主要部分的顶表面和底表面上的第一端子和第二端子。 主要部分包括第一和第二层部分，以及贯穿它们的电极。 通孔电连接到第一和第二端子。 每个层部分包括具有第一表面和与其相对的第二表面的半导体芯片，并且还包括表面电极。 表面电极设置在与第二表面相对的半导体芯片的一侧上。 第一和第二层部分彼此接合，使得相应的第二表面彼此面对。 第一端子通过使用第一层部分的表面电极形成。 第二端子通过使用第二层部分的表面电极形成。
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公开(公告)号：US08541887B2
公开(公告)日：2013-09-24
申请号：US12875710
申请日：2010-09-03
IPC分类号： H01L25/00
CPC分类号： H01L21/6835 , H01L21/563 , H01L23/3192 , H01L23/544 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/24 , H01L24/25 , H01L24/27 , H01L24/29 , H01L24/32 , H01L24/81 , H01L24/83 , H01L24/92 , H01L24/94 , H01L24/95 , H01L24/96 , H01L25/0657 , H01L25/105 , H01L25/16 , H01L25/50 , H01L2221/68327 , H01L2223/54406 , H01L2223/54433 , H01L2223/54453 , H01L2224/0231 , H01L2224/02311 , H01L2224/02313 , H01L2224/02321 , H01L2224/02371 , H01L2224/02375 , H01L2224/02379 , H01L2224/02381 , H01L2224/0239 , H01L2224/0345 , H01L2224/0346 , H01L2224/0401 , H01L2224/04026 , H01L2224/05008 , H01L2224/05644 , H01L2224/05647 , H01L2224/1146 , H01L2224/13144 , H01L2224/16148 , H01L2224/24011 , H01L2224/24145 , H01L2224/24146 , H01L2224/245 , H01L2224/2746 , H01L2224/29144 , H01L2224/2919 , H01L2224/32148 , H01L2224/81121 , H01L2224/8113 , H01L2224/81191 , H01L2224/81193 , H01L2224/81203 , H01L2224/81815 , H01L2224/82005 , H01L2224/82101 , H01L2224/82106 , H01L2224/83005 , H01L2224/8313 , H01L2224/83191 , H01L2224/83193 , H01L2224/83203 , H01L2224/83444 , H01L2224/83815 , H01L2224/8385 , H01L2224/9202 , H01L2224/92244 , H01L2224/95001 , H01L2224/96 , H01L2225/06551 , H01L2225/06558 , H01L2225/06565 , H01L2225/1058 , H01L2924/01005 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01037 , H01L2924/0105 , H01L2924/01058 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/07802 , H01L2924/3511 , H01L2924/00014 , H01L2224/81 , H01L2224/83 , H01L2924/00 , H01L2221/68304
摘要： A layered chip package includes a main body, and wiring that includes a plurality of wires disposed on a side surface of the main body. The main body includes: a main part including first and second layer portions; and a plurality of first and second terminals that are disposed on the top and bottom surfaces of the main part, respectively, and are electrically connected to the plurality of wires. Each layer portion includes a semiconductor chip having a first surface and a second surface opposite thereto, and includes a plurality of electrodes. The electrodes are disposed on a side of the semiconductor chip opposite to the second surface. The first and second layer portions are bonded to each other such that the respective second surfaces face each other. The first terminals are formed by using the electrodes of the first layer portion, and the second terminals are formed by using the electrodes of the second layer portion.
摘要翻译： 分层芯片封装包括主体和布线，其包括布置在主体的侧表面上的多根导线。 主体包括：主要部分，包括第一和第二层部分; 以及多个第一和第二端子，其分别设置在主要部分的顶表面和底表面上，并且电连接到多个导线。 每个层部分包括具有第一表面和与其相对的第二表面的半导体芯片，并且包括多个电极。 电极设置在与第二表面相对的半导体芯片的一侧上。 第一和第二层部分彼此接合，使得相应的第二表面彼此面对。 通过使用第一层部分的电极形成第一端子，并且通过使用第二层部分的电极形成第二端子。
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公开(公告)号：US08426979B2
公开(公告)日：2013-04-23
申请号：US13184971
申请日：2011-07-18
IPC分类号： H01L23/52
CPC分类号： H01L23/5389 , H01L21/6835 , H01L22/22 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/24 , H01L24/25 , H01L24/27 , H01L24/29 , H01L24/32 , H01L24/75 , H01L24/81 , H01L24/82 , H01L24/83 , H01L24/92 , H01L24/94 , H01L24/95 , H01L25/0657 , H01L25/105 , H01L25/50 , H01L2221/68327 , H01L2221/6834 , H01L2224/02311 , H01L2224/02313 , H01L2224/02321 , H01L2224/0235 , H01L2224/02371 , H01L2224/02373 , H01L2224/02379 , H01L2224/0239 , H01L2224/024 , H01L2224/0345 , H01L2224/0346 , H01L2224/0401 , H01L2224/04026 , H01L2224/05008 , H01L2224/05013 , H01L2224/05147 , H01L2224/05644 , H01L2224/1146 , H01L2224/13024 , H01L2224/13144 , H01L2224/16148 , H01L2224/24011 , H01L2224/2405 , H01L2224/24146 , H01L2224/245 , H01L2224/2512 , H01L2224/25171 , H01L2224/25175 , H01L2224/25177 , H01L2224/2746 , H01L2224/29024 , H01L2224/29144 , H01L2224/32145 , H01L2224/32148 , H01L2224/75101 , H01L2224/8112 , H01L2224/81191 , H01L2224/81203 , H01L2224/81815 , H01L2224/82101 , H01L2224/82106 , H01L2224/83005 , H01L2224/8313 , H01L2224/83191 , H01L2224/83203 , H01L2224/83815 , H01L2224/8385 , H01L2224/83986 , H01L2224/92 , H01L2224/92244 , H01L2224/94 , H01L2224/95 , H01L2225/06541 , H01L2225/06551 , H01L2225/06565 , H01L2225/1058 , H01L2225/1064 , H01L2924/07802 , H01L2924/0105 , H01L2224/82 , H01L2924/00014 , H01L2224/83 , H01L2224/11 , H01L2224/0231 , H01L2224/27 , H01L21/78 , H01L2224/81 , H01L2924/00
摘要： A composite layered chip package includes a plurality of subpackages stacked on each other. Each subpackage includes a main body and wiring. The main body includes a main part including a plurality of layer portions, and further includes first terminals and second terminals that are disposed on top and bottom surfaces of the main part, respectively. The wiring is electrically connected to the first and second terminals. The number of the plurality of layer portions included in the main part is the same for all the plurality of subpackages, and the plurality of layer portions in every subpackage include at least one first-type layer portion. In each of at least two of the subpackages, the plurality of layer portions further include at least one second-type layer portion. The first-type layer portion includes a semiconductor chip connected to the wiring, whereas the second-type layer portion includes a semiconductor chip not connected to the wiring.
摘要翻译： 复合分层芯片封装包括彼此堆叠的多个子封装。 每个子包包括主体和接线。 主体包括包括多个层部分的主要部分，并且还包括分别设置在主要部分的顶表面和底表面上的第一端子和第二端子。 布线电连接到第一和第二端子。 包括在主要部分中的多个层部分的数量对于所有多个子包是相同的，并且每个子包中的多个层部分包括至少一个第一类型层部分。 在至少两个子包中的每一个中，多个层部分还包括至少一个第二类型层部分。 第一型层部分包括连接到布线的半导体芯片，而第二型层部分包括未连接到布线的半导体芯片。
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公开(公告)号：US08344494B2
公开(公告)日：2013-01-01
申请号：US13084053
申请日：2011-04-11
CPC分类号： H01L21/561 , H01L23/3121 , H01L24/24 , H01L24/82 , H01L24/92 , H01L24/94 , H01L24/96 , H01L24/97 , H01L25/0657 , H01L25/105 , H01L25/16 , H01L25/50 , H01L2224/04105 , H01L2224/12105 , H01L2224/19 , H01L2224/24145 , H01L2224/32145 , H01L2224/73267 , H01L2224/94 , H01L2224/97 , H01L2225/06524 , H01L2225/06527 , H01L2225/06551 , H01L2225/06565 , H01L2225/1035 , H01L2225/1058 , H01L2924/07802 , H01L2924/12042 , H01L2924/18162 , H01L2924/00 , H01L2224/03 , H01L2224/83 , H01L2224/82 , H01L2224/83005
摘要： A layered chip package includes a main body and wiring. The main body includes a main part including a plurality of stacked layer portions, and a plurality of terminals disposed on the top and bottom surfaces of the main part. The wiring includes a plurality of lines electrically connected to the plurality of terminals. The plurality of lines include a plurality of common lines and a plurality of layer-dependent lines. Each of the plurality of layer portions includes: a plurality of common electrodes electrically connected to the plurality of common lines; a plurality of non-contact electrodes that are electrically connected to the layer-dependent lines and are not in contact with the semiconductor chip in the layer portion; and a selective connection electrode selectively electrically connected to only the layer-dependent line that the layer portion uses among the plurality of layer-dependent lines. The layer-dependent lines are greater than the common lines in maximum width.
摘要翻译： 分层芯片封装包括主体和布线。 主体包括主要部分，其包括多个堆叠层部分，以及设置在主要部分的顶表面和底表面上的多个端子。 布线包括电连接到多个端子的多条线。 多条线包括多条公共线和多个依赖于层的线。 多个层部分中的每一个包括：电连接到多个公共线的多个公共电极; 多个非接触电极，其电连接到与层相关的线，并且不与层部分中的半导体芯片接触; 以及选择性连接电极，其仅选择性地电连接到所述层部分在多个层相关线中使用的与层相关的线。 层相关线大于最大宽度的公共线。
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公开(公告)号：US08652877B2
公开(公告)日：2014-02-18
申请号：US12960921
申请日：2010-12-06
IPC分类号： H01L21/00
CPC分类号： H01L25/50 , H01L23/49805 , H01L24/19 , H01L24/20 , H01L24/24 , H01L24/82 , H01L24/96 , H01L24/97 , H01L25/0657 , H01L25/105 , H01L2224/24137 , H01L2225/06513 , H01L2225/06551 , H01L2225/06565 , H01L2924/07802 , H01L2924/18162 , H01L2924/00
摘要： A layered chip package includes a main body, and wiring that includes a plurality of wires disposed on a side surface of the main body. The main body includes a plurality of stacked layer portions. A method of manufacturing the layered chip package includes the step of fabricating a layered substructure and the step of cutting the layered substructure. The layered substructure includes: a plurality of arrayed pre-separation main bodies; a plurality of accommodation parts disposed between two adjacent pre-separation main bodies; and a plurality of preliminary wires accommodated in the accommodation parts. The accommodation parts are formed in a photosensitive resin layer by photolithography. In the step of cutting the layered substructure, the plurality of pre-separation main bodies are separated from each other, and the wires are formed by the preliminary wires.
摘要翻译： 分层芯片封装包括主体和布线，其包括布置在主体的侧表面上的多根导线。 主体包括多个堆叠层部分。 制造层状芯片封装的方法包括制造层状子结构的步骤和切割层状子结构的步骤。 分层子结构包括：多个排列的预分离主体; 设置在两个相邻的预分离主体之间的多个容纳部件; 以及容纳在容纳部中的多条初级线。 通过光刻在光敏树脂层中形成住宿部。 在切割层状子结构的步骤中，多个预分离主体彼此分离，并且通过初步线形成电线。
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公开(公告)号：US08421243B2
公开(公告)日：2013-04-16
申请号：US12822601
申请日：2010-06-24
IPC分类号： H01L23/52
CPC分类号： H01L21/6835 , H01L21/563 , H01L21/76898 , H01L23/522 , H01L23/544 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/24 , H01L24/25 , H01L24/27 , H01L24/29 , H01L24/32 , H01L24/81 , H01L24/82 , H01L24/83 , H01L24/92 , H01L24/94 , H01L24/95 , H01L24/96 , H01L24/97 , H01L25/0657 , H01L25/105 , H01L25/16 , H01L25/50 , H01L2221/68327 , H01L2223/54406 , H01L2223/54433 , H01L2223/54453 , H01L2224/0231 , H01L2224/02311 , H01L2224/02313 , H01L2224/02317 , H01L2224/02321 , H01L2224/02371 , H01L2224/02375 , H01L2224/02379 , H01L2224/02381 , H01L2224/0239 , H01L2224/0345 , H01L2224/0346 , H01L2224/0401 , H01L2224/04026 , H01L2224/05008 , H01L2224/05554 , H01L2224/05644 , H01L2224/05647 , H01L2224/1146 , H01L2224/13144 , H01L2224/16148 , H01L2224/24011 , H01L2224/24146 , H01L2224/245 , H01L2224/2746 , H01L2224/29144 , H01L2224/2919 , H01L2224/32148 , H01L2224/81121 , H01L2224/8113 , H01L2224/81191 , H01L2224/81193 , H01L2224/81203 , H01L2224/81815 , H01L2224/82005 , H01L2224/821 , H01L2224/82101 , H01L2224/82106 , H01L2224/83005 , H01L2224/83121 , H01L2224/8313 , H01L2224/83191 , H01L2224/83193 , H01L2224/83203 , H01L2224/83815 , H01L2224/8385 , H01L2224/85 , H01L2224/9202 , H01L2224/92244 , H01L2224/94 , H01L2224/95001 , H01L2224/96 , H01L2224/97 , H01L2225/06551 , H01L2225/06565 , H01L2225/1058 , H01L2924/01005 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/07802 , H01L2924/10253 , H01L2224/81 , H01L2224/83 , H01L2224/82 , H01L2924/00 , H01L2221/68304
摘要： A layered chip package includes a main body, and wiring disposed on a side surface of the main body. The main body includes: a main part including a plurality of layer portions stacked; a plurality of first terminals disposed on the top surface of the main part and connected to the wiring; and a plurality of second terminals disposed on the bottom surface of the main part and connected to the wiring. The plurality of layer portions include a first-type layer portion and a second-type layer portion. The first-type layer portion includes a conforming semiconductor chip, and a plurality of first-type electrodes that are connected to the semiconductor chip and the wiring. The second-type layer portion includes a defective semiconductor chip, and a plurality of second-type electrodes that are connected to the wiring and not to the semiconductor chip.
摘要翻译： 分层芯片封装包括主体和布置在主体的侧表面上的布线。 主体包括：主要部分，其包括堆叠的多个层部分; 多个第一端子，其设置在所述主体部的上表面并与所述布线连接; 以及多个第二端子，其设置在所述主体部的底面并与所述布线连接。 多个层部分包括第一类型层部分和第二类型部分。 第一型层部分包括符合半导体芯片和连接到半导体芯片和布线的多个第一类型电极。 第二型层部分包括有缺陷的半导体芯片，以及多个第二类型电极，其连接到布线而不连接到半导体芯片。
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公开(公告)号：US08203216B2
公开(公告)日：2012-06-19
申请号：US12835343
申请日：2010-07-13
IPC分类号： H01L23/48
CPC分类号： H01L24/81 , H01L21/6835 , H01L22/22 , H01L24/05 , H01L24/06 , H01L24/13 , H01L24/16 , H01L24/32 , H01L24/83 , H01L24/92 , H01L24/96 , H01L25/0657 , H01L25/105 , H01L25/50 , H01L2221/68327 , H01L2224/03002 , H01L2224/0401 , H01L2224/04105 , H01L2224/05553 , H01L2224/05644 , H01L2224/06155 , H01L2224/13144 , H01L2224/16145 , H01L2224/29144 , H01L2224/32145 , H01L2224/81815 , H01L2224/82005 , H01L2224/83005 , H01L2224/83815 , H01L2224/8385 , H01L2224/9202 , H01L2224/96 , H01L2225/06551 , H01L2225/06565 , H01L2225/1058 , H01L2924/07802 , H01L2924/1434 , H01L2224/03 , H01L2924/0105 , H01L2924/00
摘要： A layered chip package includes a main body and wiring, the wiring including a plurality of wires disposed on a side surface of the main body. The main body includes a main part and a plurality of terminals. The main part includes a plurality of layer portions stacked. The terminals are disposed on at least either one of the top and bottom surfaces of the main part and electrically connected to the wires. Each of the layer portions includes a semiconductor chip. The plurality of wires include a plurality of common wires and a plurality of layer-dependent wires. In at least one of the layer portions, the semiconductor chip is electrically connected to the plurality of common wires and is selectively electrically connected to only the layer-dependent wire that the layer portion uses, among the plurality of layer-dependent wires.
摘要翻译： 分层芯片封装包括主体和布线，所述布线包括设置在主体的侧表面上的多根布线。 主体包括主要部分和多个端子。 主要部分包括堆叠的多个层部分。 端子设置在主要部件的顶表面和底表面中的至少一个中并电连接到电线。 每个层部分包括半导体芯片。 所述多根导线包括多根公共导线和多个依赖于层的导线。 在至少一个层部分中，半导体芯片电连接到多个公共导线，并且在多个依赖于层的导线中，仅选择性地电连接到层部分使用的与层相关的导线。
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公开(公告)号：US20120013025A1
公开(公告)日：2012-01-19
申请号：US12835343
申请日：2010-07-13
CPC分类号： H01L24/81 , H01L21/6835 , H01L22/22 , H01L24/05 , H01L24/06 , H01L24/13 , H01L24/16 , H01L24/32 , H01L24/83 , H01L24/92 , H01L24/96 , H01L25/0657 , H01L25/105 , H01L25/50 , H01L2221/68327 , H01L2224/03002 , H01L2224/0401 , H01L2224/04105 , H01L2224/05553 , H01L2224/05644 , H01L2224/06155 , H01L2224/13144 , H01L2224/16145 , H01L2224/29144 , H01L2224/32145 , H01L2224/81815 , H01L2224/82005 , H01L2224/83005 , H01L2224/83815 , H01L2224/8385 , H01L2224/9202 , H01L2224/96 , H01L2225/06551 , H01L2225/06565 , H01L2225/1058 , H01L2924/07802 , H01L2924/1434 , H01L2224/03 , H01L2924/0105 , H01L2924/00
摘要： A layered chip package includes a main body and wiring, the wiring including a plurality of wires disposed on a side surface of the main body. The main body includes a main part and a plurality of terminals. The main part includes a plurality of layer portions stacked. The terminals are disposed on at least either one of the top and bottom surfaces of the main part and electrically connected to the wires. Each of the layer portions includes a semiconductor chip. The plurality of wires include a plurality of common wires and a plurality of layer-dependent wires. In at least one of the layer portions, the semiconductor chip is electrically connected to the plurality of common wires and is selectively electrically connected to only the layer-dependent wire that the layer portion uses, among the plurality of layer-dependent wires.
摘要翻译： 分层芯片封装包括主体和布线，所述布线包括设置在主体的侧表面上的多根布线。 主体包括主要部分和多个端子。 主要部分包括堆叠的多个层部分。 端子设置在主要部件的顶表面和底表面中的至少一个中并电连接到电线。 每个层部分包括半导体芯片。 所述多根导线包括多根公共导线和多个依赖于层的导线。 在至少一个层部分中，半导体芯片电连接到多个公共导线，并且在多个依赖于层的导线中，仅选择性地电连接到层部分使用的与层相关的导线。
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公开(公告)号：US08253257B2
公开(公告)日：2012-08-28
申请号：US13014418
申请日：2011-01-26
IPC分类号： H01L29/40
CPC分类号： H01L22/22 , H01L21/6835 , H01L24/05 , H01L24/13 , H01L24/16 , H01L24/32 , H01L24/92 , H01L24/96 , H01L25/0657 , H01L25/105 , H01L25/50 , H01L2221/68327 , H01L2221/6834 , H01L2224/0401 , H01L2224/04105 , H01L2224/05008 , H01L2224/05011 , H01L2224/05013 , H01L2224/05569 , H01L2224/05644 , H01L2224/06155 , H01L2224/06165 , H01L2224/13144 , H01L2224/16145 , H01L2224/32145 , H01L2224/9202 , H01L2224/96 , H01L2225/06551 , H01L2225/06565 , H01L2225/1058 , H01L2924/00014 , H01L2924/01029 , H01L2924/07802 , H01L2924/1434 , H01L2924/1436 , H01L2924/1437 , H01L2924/0105 , H01L2224/03 , H01L2924/00 , H01L2224/05552
摘要： A layered chip package includes a main body and wiring. The main body includes a main part including a plurality of stacked layer portions, and a plurality of terminals disposed on the top and bottom surfaces of the main part. The wiring includes a plurality of lines electrically connected to the plurality of terminals. The plurality of lines include a plurality of common lines and a plurality of layer-dependent lines. Each of the plurality of layer portions includes a plurality of common electrodes electrically connected to the plurality of common lines, and a selective connection electrode selectively electrically connected to only the layer-dependent line that the layer portion uses among the plurality of layer-dependent lines. The selective connection electrode varies in shape depending on which of the layer-dependent lines it is electrically connected to.
摘要翻译： 分层芯片封装包括主体和布线。 主体包括主要部分，其包括多个堆叠层部分，以及设置在主要部分的顶表面和底表面上的多个端子。 布线包括电连接到多个端子的多条线。 多条线包括多条公共线和多个依赖于层的线。 多个层部分中的每一个包括电连接到多个公共线的多个公共电极，以及选择性连接电极，其选择性地电连接到多个层相关线之间的层部分使用的与层相关的线 。 选择性连接电极根据与电连接的层相关线路的形状而变化。
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