公开(公告)号：US20250117139A1

公开(公告)日：2025-04-10

申请号：US18984029

申请日：2024-12-17

Applicant: SUNRISE MEMORY CORPORATION

Inventor： Shay Fux ,  Sagie Goldenberg ,  Amotz Yagev

IPC: G06F3/06

Abstract: A control circuit is configured to interact with a memory device to perform read and write operation at the memory device where the memory device includes memory transistors organized in a set of tiles. The control circuit includes a read queue configured to store active read requests for reading data from the memory device, each active read request being addressed to a respective tile in the set of tiles; a write queue configured to store active write requests for writing data to the memory device, each active write request being addressed to a respective tile in the set of tiles; and a write staging buffer configured to store pending write requests received by the control circuit and to transfer the pending write requests to the write queue to maximize a number of the active write requests in the write queue that are addressed to different tiles of the memory device.

公开(公告)号：US12256547B2

公开(公告)日：2025-03-18

申请号：US17494549

申请日：2021-10-05

Applicant: SUNRISE MEMORY CORPORATION

Inventor： Scott Brad Herner ,  Christopher J. Petti ,  George Samachisa ,  Wu-Yi Henry Chien

IPC: H10B43/35 ,  G11C16/04 ,  H10B43/20

Abstract: A thin-film storage transistor in a NOR memory string has a gate dielectric layer that includes a silicon oxide nitride (SiON) tunnel dielectric layer. In one embodiment, the SiON tunnel dielectric layer has a thickness between 0.5 to 5.0 nm thick and an index of refraction between 1.5 and 1.9. The SiON tunnel dielectric layer may be deposited at between 720° C. and 900° C. and between 100 and 800 mTorr vapor pressure, using an LPCVD technique under DCS, N2O, and NH3 gas flows. The SiON tunnel dielectric layer may have a nitrogen content of 1-30 atomic percent (at %).

公开(公告)号：US20250087281A1

公开(公告)日：2025-03-13

申请号：US18957329

申请日：2024-11-22

Applicant: SUNRISE MEMORY CORPORATION

Inventor： Eli Harari

IPC: G11C16/34 ,  G06F17/16 ,  G06N3/063 ,  G11C11/56 ,  G11C16/04 ,  G11C16/10 ,  H01L21/28 ,  H01L29/08 ,  H01L29/10 ,  H01L29/66 ,  H01L29/786 ,  H01L29/792 ,  H01L29/92 ,  H10B43/10 ,  H10B43/27

Abstract: A 3-dimensional array of NOR memory strings being organized by planes of NOR memory strings, in which (i) the storage transistors in the NOR memory strings situated in a first group of planes are configured to be programmed, erased, program-inhibited or read in parallel, and (ii) the storage transistors in NOR memory strings situated within a second group of planes are configured for storing resource management data relating to data stored in the storage transistors of the NOR memory strings situated within the first group of planes, wherein the storage transistors in NOR memory strings in the second group of planes are configured into sets.

公开(公告)号：US12096630B2

公开(公告)日：2024-09-17

申请号：US16577469

申请日：2019-09-20

Applicant: SUNRISE MEMORY CORPORATION

Inventor： Raul Adrian Cernea ,  Wu-Yi Henry Chien ,  Eli Harari

IPC: H10B43/20 ,  H01L21/285 ,  H01L21/306 ,  H01L21/3213 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H10B43/30

CPC classification number: H10B43/20 ,  H01L21/28525 ,  H01L21/30604 ,  H01L21/32133 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53271 ,  H10B43/30

Abstract: Various methods and various staircase structures formed out of the active strips of a memory structure (e.g., a memory array having a three-dimensional arrangement of NOR memory strings) above a semiconductor substrate allows efficient electrical connections to semiconductor layers within the active strips.

公开(公告)号：US12073082B2

公开(公告)日：2024-08-27

申请号：US18306073

申请日：2023-04-24

Applicant: SUNRISE MEMORY CORPORATION

Inventor： Youn Cheul Kim ,  Richard S. Chernicoff ,  Khandker Nazrul Quader ,  Robert D. Norman ,  Tianhong Yan ,  Sayeef Salahuddin ,  Eli Harari

IPC: G11C11/00 ,  G06F3/06 ,  H01L23/00 ,  H01L25/18

CPC classification number: G06F3/0611 ,  G06F3/0631 ,  H01L24/20 ,  H01L25/18 ,  H01L2224/211 ,  H01L2224/214 ,  H01L2924/1431 ,  H01L2924/1435

Abstract: A first circuit formed on a first semiconductor substrate is wafer-bonded to a second circuit formed on a second memory circuit, wherein the first circuit includes quasi-volatile or non-volatile memory circuits and wherein the second memory circuit includes fast memory circuits that have lower read latencies than the quasi-volatile or non-volatile memory circuits, as well as logic circuits. The volatile and non-volatile memory circuits may include static random-access memory (SRAM) circuits, dynamic random-access memory (DRAM) circuits, embedded DRAM (eDRAM) circuits, magnetic random-access memory (MRAM) circuits, embedded MRAM (eMRAM), or any suitable combination of these circuits.

公开(公告)号：US20240179919A1

公开(公告)日：2024-05-30

申请号：US18436365

申请日：2024-02-08

Applicant: SunRise Memory Corporation

Inventor： Tianhong Yan ,  Scott Brad Herner ,  Jie Zhou ,  Wu-Yi Henry Chien ,  Eli Harari

IPC: H10B43/40 ,  H01L21/02 ,  H01L21/225 ,  H01L21/311 ,  H01L21/3205 ,  H01L23/528 ,  H01L29/45 ,  H01L29/66 ,  H01L29/786 ,  H10B43/10 ,  H10B43/27

CPC classification number: H10B43/40 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/2251 ,  H01L21/31111 ,  H01L21/32053 ,  H01L23/528 ,  H01L29/458 ,  H01L29/665 ,  H01L29/66742 ,  H01L29/78642 ,  H10B43/10 ,  H10B43/27

Abstract: A memory circuit includes: (i) a semiconductor substrate having a planar surface, the semiconductor substrate having formed therein circuitry for memory operations; (ii) a memory array formed above the planar surface, the memory array having one or more electrodes to memory circuits in the memory array, the conductors each extending along a direction substantially parallel to the planar surface; and (iii) one or more transistors each formed above, alongside or below a corresponding one of the electrodes but above the planar surface of the semiconductor substrate, each transistor (a) having first and second drain/source region and a gate region each formed out of a semiconductor material, wherein the first drain/source region, the second drain/source region or the gate region has formed thereon a metal silicide layer; and (b) selectively connecting the corresponding electrode to the circuitry for memory operations.

公开(公告)号：US20240161837A1

公开(公告)日：2024-05-16

申请号：US18420073

申请日：2024-01-23

Applicant: SUNRISE MEMORY CORPORATION

Inventor： Eli Harari

IPC: G11C16/34 ,  G06F17/16 ,  G06N3/063 ,  G11C11/56 ,  G11C16/04 ,  G11C16/10 ,  H01L21/28 ,  H01L29/08 ,  H01L29/10 ,  H01L29/66 ,  H01L29/786 ,  H01L29/792 ,  H01L29/92 ,  H10B43/27

CPC classification number: G11C16/3431 ,  G06F17/16 ,  G06N3/063 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/5642 ,  G11C16/0416 ,  G11C16/0466 ,  G11C16/0483 ,  G11C16/0491 ,  G11C16/10 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/40117 ,  H01L29/66833 ,  H01L29/78633 ,  H01L29/7926 ,  H01L29/92 ,  H10B43/27 ,  H10B43/10

Abstract: A 3-dimensional array of NOR memory strings being organized by planes of NOR memory strings, in which (i) the storage transistors in the NOR memory strings situated in a first group of planes are configured to be programmed, erased, program-inhibited or read in parallel, and (ii) the storage transistors in NOR memory strings situated within a second group of planes are configured for storing resource management data relating to data stored in the storage transistors of the NOR memory strings situated within the first group of planes, wherein the storage transistors in NOR memory strings in the second group of planes are configured into sets.

公开(公告)号：US11968837B2

公开(公告)日：2024-04-23

申请号：US18049979

申请日：2022-10-26

Applicant: SUNRISE MEMORY CORPORATION

Inventor： Scott Brad Herner

IPC: H10B43/27 ,  H01L29/08 ,  H01L29/792 ,  H10B43/20 ,  H10B43/30

CPC classification number: H10B43/27 ,  H01L29/0847 ,  H10B43/20 ,  H10B43/30 ,  H01L29/7923

Abstract: A staggered memory cell architecture staggers memory cells on opposite sides of a shared bit line preserves memory cell density, while increasing the distance between such memory cells, thereby reducing the possibility of a disturb. In one implementation, the memory cells along a first side of a shared bit line are connected to a set of global word lines provided underneath the memory structure, while the memory cells on the other side of the shared bit line—which are staggered relative to the memory cells on the first side—are connected to global word lines above the memory structure.

公开(公告)号：US20240045796A1

公开(公告)日：2024-02-08

申请号：US18229060

申请日：2023-08-01

Applicant: SUNRISE MEMORY CORPORATION

Inventor： Shay Fux ,  Amotz Yagev ,  Sagie Goldenberg

IPC: G06F12/02 ,  G06F12/1009 ,  G06F11/07

CPC classification number: G06F12/0246 ,  G06F12/1009 ,  G06F11/0772 ,  G06F2212/7211

Abstract: A memory device includes: (a) one or more memory circuits having physical memory pages identified by physical page addresses, each physical memory page being provided to store a memory page; and (b) a control circuit configured for managing read or write operations in each memory circuit. The control circuit manages both a wear-leveling scheme and read and write operations in the memory circuits.

公开(公告)号：US11848056B2

公开(公告)日：2023-12-19

申请号：US17529083

申请日：2021-11-17

Applicant: SUNRISE MEMORY CORPORATION

Inventor： Raul Adrian Cernea

IPC: G11C16/26 ,  G11C16/08 ,  G11C16/24

CPC classification number: G11C16/26 ,  G11C16/08 ,  G11C16/24

Abstract: A semiconductor memory device is implemented as a string of storage transistors with sense amplifier connected drain terminals and floating source terminals. In some embodiments, a method in the semiconductor memory device applies a bit line control (BLC) voltage with a voltage step down to the bias device during the read operation to reduce the settling time on the bit line, thereby shortening the access time for data read out from the storage transistors. In other embodiments, a method in the semiconductor memory device including an array of strings of storage transistors uses a current from a biased but unselected bit line as the sense amplifier reference current for reading stored data from a selected bit line. In one embodiment, the sense amplifier reference current is provided to a referenced sense amplifier to generate a sense amplifier data latch signal.