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    NAND STRING READ VOLTAGE ADJUSTMENT
    92.
    发明公开
    NAND STRING READ VOLTAGE ADJUSTMENT 审中-公开

    公开(公告)号：US20240086074A1

    公开(公告)日：2024-03-14

    申请号：US17940465

    申请日：2022-09-08

    Applicant: SanDisk Technologies LLC

    Inventor： Yi Song ,  Jiahui Yuan ,  Yanjie Wang

    IPC: G06F3/06

    CPC classification number: G06F3/0619 ,  G06F3/0653 ,  G06F3/0679

    Abstract: An apparatus includes a control circuit configured to connect to NAND strings that are connected to bit lines, where each bit line is connected to a plurality of NAND strings in a corresponding plurality of regions of a block. The control circuit is configured to apply a read voltage in read operations directed to NAND strings of the plurality of regions of the block and subsequently adjust the read voltage by a first predetermined amount for read operations directed to NAND strings of a first region of the block. The control circuit is further configured to adjust the read voltage by a second predetermined amount for read operations directed to NAND strings of a second region of the block. The first and second predetermined amounts are based on respective locations of the first and second regions in the block.

    DUAL-WAY SENSING SCHEME FOR BETTER NEIGHBORING WORD-LINE INTERFERENCE
    93.
    发明公开
    DUAL-WAY SENSING SCHEME FOR BETTER NEIGHBORING WORD-LINE INTERFERENCE 审中-公开

    公开(公告)号：US20240079068A1

    公开(公告)日：2024-03-07

    申请号：US17939748

    申请日：2022-09-07

    Applicant: SanDisk Technologies LLC

    Inventor： Dengtao Zhao ,  Deepanshu Dutta ,  Peng Zhang ,  Heguang Li

    IPC: G11C16/34 ,  G11C16/10 ,  G11C16/26

    CPC classification number: G11C16/3427 ,  G11C16/10 ,  G11C16/26

    Abstract: A storage device is disclosed herein. The storage device comprises: a non-volatile memory, where the non-volatile memory includes a block of N wordlines partitioned into a plurality of sub-blocks and the plurality of sub-blocks includes a first sub-block of a first subset of the block of N wordlines and a second sub-block of a second subset of the block of N wordlines; and control circuitry coupled to the block of N wordlines. The control circuitry is configured to: perform a program operation in a normal order programming sequence on the first sub-block; perform a sensing operation on the first sub-block using a reverse sensing scheme; perform a program operation in a reverse order programming sequence on the second sub-block; and perform a sensing operation on the second sub-block using a regular sensing scheme.

    DYNAMIC WORD LINE BOOSTING DURING PROGRAMMING OF A MEMORY DEVICE
    94.
    发明公开
    DYNAMIC WORD LINE BOOSTING DURING PROGRAMMING OF A MEMORY DEVICE 审中-公开

    公开(公告)号：US20240079063A1

    公开(公告)日：2024-03-07

    申请号：US17939160

    申请日：2022-09-07

    Applicant: SanDisk Technologies LLC

    Inventor： Han-Ping Chen ,  Yanjie Wang

    IPC: G11C16/10 ,  G11C16/04

    CPC classification number: G11C16/10 ,  G11C16/0483

    Abstract: The memory device includes a memory block, which includes a plurality of memory cells arranged in a plurality of word lines. The memory device also includes control circuitry in communication with the memory block. The control circuitry is configured to perform a programming operation to program the memory cells of a selected word line of the plurality of word lines. During the programming operation, the control circuitry is configured to apply a programming pulse VPGM to a selected word line to the selected word line, apply a first pass voltage to a first set of word lines of the plurality of word lines, the first set of word lines being adjacent the selected word line, and apply a second pass voltage to a second set of word lines of the plurality of word. The first pass voltage is greater than the second pass voltage.

    FOGGY-FINE DRAIN-SIDE SELECT GATE RE-PROGRAM FOR ON-PITCH SEMI-CIRCLE DRAIN SIDE SELECT GATES
    95.
    发明公开
    FOGGY-FINE DRAIN-SIDE SELECT GATE RE-PROGRAM FOR ON-PITCH SEMI-CIRCLE DRAIN SIDE SELECT GATES 审中-公开

    公开(公告)号：US20240079061A1

    公开(公告)日：2024-03-07

    申请号：US17901197

    申请日：2022-09-01

    Applicant: SanDisk Technologies LLC

    Inventor： Xiaoyu Che ,  Yanjie Wang

    IPC: G11C16/10 ,  G11C16/04 ,  G11C16/16

    CPC classification number: G11C16/10 ,  G11C16/0483 ,  G11C16/16

    Abstract: A memory apparatus and method of operation are provided. The apparatus includes drain-side select gate transistors for coupling to a drain-side of memory holes of memory cells and configured to retain a transistor threshold voltage. The memory holes are arranged in rows comprising strings. A control means is configured to program drain-side select gate transistors of the memory holes to an initial transistor threshold voltage using pulses increasing in magnitude by a first transistor step amount during each of a plurality of foggy loops of a foggy program operation. The control means is also configured to program the drain-side select gate transistors of the memory holes to a target transistor threshold voltage using pulses increasing in magnitude by a second transistor step amount during each of a plurality of fine loops of a fine program operation. The first transistor step amount is greater than the second transistor step amount.

    TWO-STAGE HIGH SPEED LEVEL SHIFTER
    97.
    发明公开
    TWO-STAGE HIGH SPEED LEVEL SHIFTER 审中-公开

    公开(公告)号：US20240072804A1

    公开(公告)日：2024-02-29

    申请号：US17898263

    申请日：2022-08-29

    Applicant: SanDisk Technologies LLC

    Inventor： SHIV HARIT MATHUR ,  SAI RAVI TEJA KONAKALLA

    IPC: H03K19/0185 ,  H03K3/037

    CPC classification number: H03K19/018521 ,  H03K3/037

    Abstract: Improved voltage level shifters are disclosed capable of achieving substantially higher data transfer speeds with reduced static current than existing cross-coupled voltage level shifters. The voltage level shifters disclosed herein include first stage that translates input voltage signals received from a core circuitry in a first voltage domain to intermediate output voltage signals an intermediate voltage domain, and second stage circuitry that translates the intermediate output voltage signals received from the first stage circuitry in the intermediate voltage domain to output voltage signals in a second voltage domain. The disclosed voltage level shifters are scalable to support various logic voltage levels in the second voltage domain.

    THREE-DIMENSIONAL MEMORY DEVICE INCLUDING LOW-K DRAIN-SELECT-LEVEL ISOLATION STRUCTURES AND METHODS OF FORMING THE SAME
    98.
    发明公开
    THREE-DIMENSIONAL MEMORY DEVICE INCLUDING LOW-K DRAIN-SELECT-LEVEL ISOLATION STRUCTURES AND METHODS OF FORMING THE SAME 审中-公开

    公开(公告)号：US20240064985A1

    公开(公告)日：2024-02-22

    申请号：US18386456

    申请日：2023-11-02

    Applicant: SANDISK TECHNOLOGIES LLC

    Inventor： Masanori Tsutsumi ,  Kazuki Isozumi ,  Peng Zhang

    IPC: H10B43/35 ,  H10B41/27 ,  H10B41/35 ,  H10B43/27

    CPC classification number: H10B43/35 ,  H10B41/27 ,  H10B41/35 ,  H10B43/27

    Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate. The electrically conductive layers include word-line-level electrically conductive layers and drain-select-level electrically conductive layers overlying the word-line-level electrically conductive layers. An array of memory opening fill structures is located within an array of memory openings vertically extending through the alternating stack. An encapsulated cavity vertically extends through the drain-select-level electrically conductive layers. The array of memory opening fill structures includes two rows of first memory opening fill structures that are arranged along a first horizontal direction. Each of the first memory opening fill structures includes a respective planar straight sidewall in contact with a respective portion of a pair of straight sidewalls of the encapsulated cavity.

    TRANSISTOR CIRCUITS INCLUDING FRINGELESS TRANSISTORS AND METHOD OF MAKING THE SAME
    99.
    发明公开
    TRANSISTOR CIRCUITS INCLUDING FRINGELESS TRANSISTORS AND METHOD OF MAKING THE SAME 审中-公开

    公开(公告)号：US20240063278A1

    公开(公告)日：2024-02-22

    申请号：US18500623

    申请日：2023-11-02

    Applicant: SANDISK TECHNOLOGIES LLC

    Inventor： Dai IWATA ,  Hokuto KODATE

    IPC: H01L29/423 ,  H01L27/06 ,  H01L29/66 ,  H01L29/06

    CPC classification number: H01L29/42364 ,  H01L27/0617 ,  H01L29/6656 ,  H01L29/0653

    Abstract: A lateral extent of a gate electrode of a field effect transistor along a gate electrode direction that is perpendicular to a channel direction can be the same as a width of an underlying active region. A gate electrode of an additional field effect transistor may extend over a trench isolation structure that laterally surrounds the additional field effect transistor. Different types of electrodes may be formed by patterning a lower gate material layer and by patterning an upper gate material layer with different patterns such that patterned portions of the lower gate material layer are confined within areas of active regions, while patterned portions of the upper gate material layer extends outside of the areas of the active regions.

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