Method for stripping copper in damascene interconnects
    91.
    发明授权
    Method for stripping copper in damascene interconnects 失效
    在大马士革互连中剥离铜的方法

    公开(公告)号:US06394114B1

    公开(公告)日:2002-05-28

    申请号:US09442312

    申请日:1999-11-22

    CPC classification number: H01L21/32134 C23F1/34 H01L21/7684 Y10S134/902

    Abstract: An inexpensive and safe copper removal method in the fabrication of integrated circuits is described. Copper is stripped or removed by a chemical mixture comprising an ammonium salt, an amine, and water. The rate of copper stripping can be controlled by varying the concentration of the ammonium salt component and the amount of water in the mixture. Also a novel chemical mixture for stripping copper and removing copper contamination is provided. The novel chemical mixture for removing or stripping copper comprises an ammonium salt, an amine, and water. For example, the novel chemical mixture may comprise ammonium fluoride, water, and ethylenediamine in a ratio of 1:1:1.

    Abstract translation: 描述了在制造集成电路中的便宜且安全的铜去除方法。 通过包含铵盐,胺和水的化学混合物将铜剥离或除去。 可以通过改变铵盐组分的浓度和混合物中的水量来控制铜汽提速率。 还提供了一种用于剥离铜并除去铜污染物的新型化学混合物。 用于除去或剥离铜的新型化学混合物包括铵盐,胺和水。 例如,新型化学混合物可以包含比例为1:1:1的氟化铵,水和乙二胺。

    Method to remove copper contamination by using downstream oxygen and chelating agent plasma
    94.
    发明授权
    Method to remove copper contamination by using downstream oxygen and chelating agent plasma 失效
    使用下游氧和螯合剂等离子体去除铜污染的方法

    公开(公告)号:US06350689B1

    公开(公告)日:2002-02-26

    申请号:US09839962

    申请日:2001-04-23

    Abstract: A method of removing copper contamination from a semiconductor wafer, comprising the following steps. A semiconductor wafer having copper contamination thereon is provided. An oxidizing radical containing downstream plasma is provided from a first source (alternatively halogen (F2, Cl2, or Br2) may be used as on oxidizing agent). A vaporized chelating agent is provided from a second source. The oxidizing radical containing downstream plasma and vaporized chelating agent are mixed to form an oxidizing radical containing downstream plasma/vaporized chelating agent mixture. The mixture is directed to the copper contamination so that the mixture reacts with the copper contamination to form a volatile product. The volatile product is removed from the proximity of the wafer.

    Abstract translation: 一种从半导体晶片去除铜污染的方法,包括以下步骤。 提供其上具有铜污染的半导体晶片。 从第一来源提供含有下游等离子体的氧化基团(或者可以在氧化剂上使用卤素(F2,Cl2或Br2))。 从第二来源提供蒸发的螯合剂。 将含有下游等离子体和气化螯合剂的氧化基团混合以形成含有下游等离子体/汽化螯合剂混合物的氧化基团。 混合物被引导到铜污染物,使得混合物与铜污染物反应形成挥发性产物。 从晶片附近去除挥发性产物。

    Semiconductor device having an intermetallic layer on metal interconnects
    97.
    发明授权
    Semiconductor device having an intermetallic layer on metal interconnects 有权
    在金属互连上具有金属间层的半导体器件

    公开(公告)号:US06172421B2

    公开(公告)日:2001-01-09

    申请号:US09132282

    申请日:1998-08-11

    CPC classification number: H01L21/76858 H01L21/76849 H01L21/76886

    Abstract: The present invention relates to the formation of a protective intermetallic layer 15 on the surface of damascene metal interconnects 12 during semiconductor fabrication. The intermetallic layer 15 prevents problems associated with formation of an oxide layer on the surface of the interconnect. The intermetallic layer is formed by depositing a metal on the surface of the interconnect that will both reduce any present metal oxide layer and form an intermetallic with the interconnect metal.

    Abstract translation: 本发明涉及在半导体制造期间在镶嵌金属互连件12的表面上形成保护性金属间化合物层15。 金属间层15防止与互连表面上形成氧化物层有关的问题。 金属间化合物层通过在互连表面上沉积金属而形成,该金属将既减少任何存在的金属氧化物层并与互连金属形成金属间化合物。

    Subtractive dual damascene semiconductor device
    98.
    发明授权
    Subtractive dual damascene semiconductor device 失效
    减法双镶嵌半导体器件

    公开(公告)号:US6051882A

    公开(公告)日:2000-04-18

    申请号:US905974

    申请日:1997-08-05

    Abstract: A method of fabricating an interconnection level of conductive lines and connecting vias separated by insulation for integrated circuits and substrate carriers for semiconductor devices using a reverse damascene in the formation of the conductive lines and vias. A conductive line pattern is first used to etch completely through the layer to form conductive line openings. The openings are completely filled with a conductive material and planarized so that the surfaces of the conductive material and the insulating layer are coplanar. A via pattern is aligned perpendicular to the conductive lines and the conductive material is etched half way through the conductive lines in other than the areas covered by the via pattern. The openings thus created in the upper portion of the conductive lines are filled with insulating material to complete the dual damascene interconnection level with the conductive lines in the lower portion of the insulating layer and upwardly projecting vias in the upper portion of the layer. In addition, a triple damascene layer is formed by starting with an insulating layer about one-third thicker than normal and by combining the standard dual damascene method with the above described method. The resulting interconnection level structure comprises conductive lines having upwardly and downwardly projecting vias.

    Abstract translation: 一种制造导线的互连电平的方法,以及用于集成电路的绝缘和用于半导体器件的衬底载体分离的通孔的方法,其使用反向镶嵌来形成导电线和通孔。 首先使用导电线图案来完全蚀刻该层以形成导电线开口。 开口完全被导电材料填充并平坦化,使得导电材料和绝缘层的表面是共面的。 通孔图案垂直于导电线对齐,并且导电材料被除了通孔图案覆盖的区域之外的一半蚀刻通过导电线。 由此在导电线的上部形成的开口用绝缘材料填充,以完成与绝缘层下部的导电线和层的上部向上突出的通孔的双镶嵌互连水平。 此外,通过从绝对层开始比正常厚约三分之一的厚度并通过将标准双镶嵌方法与上述方法组合来形成三镶嵌层。 所产生的互连级联结构包括具有向上和向下突出的通孔的导线。

    Method of forming a high conductivity metal interconnect using metal
gettering plug and system performing the method
    99.
    发明授权
    Method of forming a high conductivity metal interconnect using metal gettering plug and system performing the method 失效
    使用金属吸气塞形成高导电性金属互连的方法和执行该方法的系统

    公开(公告)号:US5994206A

    公开(公告)日:1999-11-30

    申请号:US944170

    申请日:1997-10-06

    CPC classification number: H01L21/76877 H01L21/76802

    Abstract: A method and system for providing a via structure for a high conductivity metal of a integrated circuit is disclosed. In a first aspect the method and system comprises etching a photoresist material and a dielectric material down to the high conductivity metal to form a via hole. The via hole includes sputtered high conductivity metal on the sidewalls. The method and system further includes providing a via plug material within the via hole. The vial plug material substantially covers a base portion of the high conductivity metal and the sidewalls of the via hole. The via plug material is also capable of gettering or dissolving the high conductivity metal sputtered on the sidewalls of the dielectric material. In a second aspect, a via structure for an integrated circuit is disclosed in accordance with the present invention. The via structure includes a high conductivity metal and a dielectric material surrounding the high conductivity metal. The dielectric material includes sidewalls to form a via hole on tope of the high conductivity metal. The via structure further includes a via plug material covering the high conductivity metal and substantially filling the via hole. The via plug material is also capable of gettering or dissolving the high conductivity metal sputtered on the sidewalls of the via hole. Accordingly, by providing a via plug material within the via hole, the via plug material getters or dissolves the high conductivity metal that reaches the sidewalls of the dielectric layer during the via etch and sputter etch processes and the junction poisoning problems associated therewith are substantially minimized.

    Abstract translation: 公开了一种用于为集成电路的高导电性金属提供通孔结构的方法和系统。 在第一方面,该方法和系统包括将光致抗蚀剂材料和电介质材料蚀刻到高导电性金属上以形成通孔。 通孔包括在侧壁上的溅射的高导电性金属。 该方法和系统还包括在通孔内提供通孔塞材料。 小瓶插头材料基本上覆盖高导电性金属的基部和通孔的侧壁。 通孔插塞材料还能够吸收或溶解溅射在电介质材料的侧壁上的高导电性金属。 在第二方面中,根据本发明公开了一种用于集成电路的通孔结构。 通孔结构包括高导电性金属和围绕高导电性金属的介电材料。 电介质材料包括在高导电性金属的顶部上形成通孔的侧壁。 通孔结构还包括覆盖高导电性金属并基本上填充通孔的通孔塞材料。 通孔插塞材料还能够吸收或溶解溅射在通孔的侧壁上的高导电性金属。 因此,通过在通孔内提供通孔插塞材料,通孔插塞材料在通孔蚀刻和溅射蚀刻工艺期间吸收或溶解到达介电层侧壁的高导电性金属,并且与之相关的结中毒问题基本上最小化 。

    Run-to-run control process for controlling critical dimensions
    100.
    发明授权
    Run-to-run control process for controlling critical dimensions 失效
    用于控制关键尺寸的运行控制过程

    公开(公告)号:US5926690A

    公开(公告)日:1999-07-20

    申请号:US864489

    申请日:1997-05-28

    CPC classification number: H01L22/20

    Abstract: It has been discovered that all causes of critical dimension variation, both known and unknown, are compensated by adjusting the time of photoresist etch. Accordingly, a control method employs a control system using photoresist etch time as a manipulated variable in either a feedforward or a feedback control configuration to control critical dimension variation during semiconductor fabrication. By controlling critical dimensions through the adjustment of photoresist etch time, many advantages are achieved including a reduced lot-to-lot variation, an increased yield, and increased speed of the fabricated circuits. In one embodiment these advantages are achieved for polysilicon gate critical dimension control in microprocessor circuits. Polysilicon gate linewidth variability is reduced using a control method using either feedforward and feedback or feedback alone. In some embodiments, feedback control is implemented for controlling critical dimensions using photoresist etch time as a manipulated variable. In an alternative embodiment, critical dimensions are controlled using RF power as a manipulated variable. A run-to-run control technique is used to drive the critical dimensions of integrated circuits to a set specification. In a run-to-run control technique a wafer test or measurement is made and a process control recipe is adjusted based on the result of the test or measurement on a run-by-run basis. The run-to-run control technique is applied to drive the critical dimensions of a polysilicon gate structure to a target specification. The run-to-run control technique is applied to drive the critical dimensions in an integrated circuit to a defined specification using photoresist etch time as a manipulated variable.

    Abstract translation: 已经发现,已知和未知的关键尺寸变化的所有原因通过调整光致抗蚀剂蚀刻的时间来补偿。 因此,控制方法采用使用光致抗蚀剂蚀刻时间的控制系统作为前馈或反馈控制配置中的操纵变量来控制半导体制造期间的临界尺寸变化。 通过调整光致抗蚀剂蚀刻时间来控制关键尺寸,实现了许多优点,包括减少的批次批量变化,增加的产量和增加的制造电路的速度。 在一个实施例中,对微处理器电路中的多晶硅栅极关键尺寸控制实现了这些优点。 使用仅使用前馈和反馈或反馈的控制方法来减少多晶硅栅极线宽变化。 在一些实施例中,实施反馈控制以使用光致抗蚀剂蚀刻时间来控制临界尺寸作为操纵变量。 在替代实施例中,使用RF功率作为操纵变量来控制临界尺寸。 运行运行控制技术用于将集成电路的关键尺寸驱动到设定规格。 在运行到运行的控制技术中,进行晶片测试或测量,并且基于逐个运行的测试或测量的结果来调整过程控制配方。 运行运行控制技术用于将多晶硅栅极结构的关键尺寸驱动到目标规格。 应用运行控制技术将集成电路中的关键尺寸驱动到使用光刻胶蚀刻时间作为操作变量的规定规格。

Patent Agency Ranking