公开(公告)号：US06198142B1

公开(公告)日：2001-03-06

申请号：US09127349

申请日：1998-07-31

申请人： Robert S. Chau ,  Chia-Hong Jan ,  Paul Packan ,  Mitchell C. Taylor

发明人： Robert S. Chau ,  Chia-Hong Jan ,  Paul Packan ,  Mitchell C. Taylor

IPC分类号： H01L2976

CPC分类号： H01L29/66636 ,  H01L21/26533 ,  H01L29/0653 ,  H01L29/165 ,  H01L29/665 ,  H01L29/66537 ,  H01L29/7834

摘要： A novel MOS transistor having minimal junction capacitance in this method of fabrication. According to the present invention, a gate dielectric layer is formed on a first surface of the semiconductor substrate. A gate electrode is then formed on the gate dielectric layer. Next, a pair of recesses are formed in the semiconductor substrate on opposite sides of the gate electrode. A dielectric layer is then formed on the surface of each of the recesses. A Semiconductor material is then deposited into the recesses to form a pair of source/drain regions.

摘要翻译： 在该制造方法中具有最小结电容的新型MOS晶体管。 根据本发明，在半导体衬底的第一表面上形成栅介质层。 然后在栅极电介质层上形成栅电极。 接下来，在栅电极的相对侧上的半导体衬底中形成一对凹部。 然后在每个凹部的表面上形成介电层。 然后将半导体材料沉积到凹槽中以形成一对源极/漏极区域。

公开(公告)号：US5908313A

公开(公告)日：1999-06-01

申请号：US775410

申请日：1996-12-31

申请人： Robert S. Chau ,  Chia-Hong Jan ,  Paul Packan ,  Mitchell C. Taylor

发明人： Robert S. Chau ,  Chia-Hong Jan ,  Paul Packan ,  Mitchell C. Taylor

IPC分类号： H01L21/225 ,  H01L21/265 ,  H01L21/28 ,  H01L21/336 ,  H01L29/06 ,  H01L29/10 ,  H01L29/417 ,  H01L29/49

CPC分类号： H01L29/66477 ,  H01L21/26586 ,  H01L21/28052 ,  H01L29/0653 ,  H01L29/1083 ,  H01L29/41766 ,  H01L29/41783 ,  H01L29/4925 ,  H01L29/66628 ,  H01L29/66636 ,  H01L21/2254 ,  H01L21/2257 ,  H01L21/26506

摘要： A novel MOS transistor having minimal junction capacitance in this method of fabrication. According to the present invention, a gate dielectric layer is formed on a first surface of the semiconductor substrate. A gate electrode is then formed on the gate dielectric layer. Next, a pair of recesses are formed in the semiconductor substrate on opposite sides of the gate electrode. A dielectric layer is then formed on the surface of each of the recesses. A Semiconductor material is then deposited into the recesses to form a pair of source/drain regions.

摘要翻译： 在该制造方法中具有最小结电容的新型MOS晶体管。 根据本发明，在半导体衬底的第一表面上形成栅介质层。 然后在栅极电介质层上形成栅电极。 接下来，在栅电极的相对侧上的半导体衬底中形成一对凹部。 然后在每个凹部的表面上形成介电层。 然后将半导体材料沉积到凹槽中以形成一对源极/漏极区域。

公开(公告)号：US5783478A

公开(公告)日：1998-07-21

申请号：US639776

申请日：1996-04-29

申请人： Robert S. Chau ,  David B. Fraser ,  Kenneth C. Cadien ,  Gopal Raghavan ,  Leopoldo D. Yau

发明人： Robert S. Chau ,  David B. Fraser ,  Kenneth C. Cadien ,  Gopal Raghavan ,  Leopoldo D. Yau

IPC分类号： H01L29/43 ,  H01L21/28 ,  H01L21/336 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78 ,  H01L21/3205

CPC分类号： H01L29/6659 ,  H01L21/2807 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/28097 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/4975 ,  H01L29/665 ,  H01L29/78 ,  H01L2924/0002

摘要： A novel, reliable, high performance MOS transistor with a composite gate electrode which is compatible with standard CMOS fabrication processes. The composite gate electrode comprises a polysilicon layer formed on a highly conductive layer. The composite gate electrode is formed on a gate insulating layer which is formed on a silicon substrate. A pair of source/drain regions are formed in the substrate and are self-aligned to the outside edges of the composite gate electrode.

摘要翻译： 一种具有与标准CMOS制造工艺兼容的复合栅电极的新颖可靠的高性能MOS晶体管。 复合栅电极包括形成在高导电层上的多晶硅层。 复合栅电极形成在形成在硅衬底上的栅极绝缘层上。 在衬底中形成一对源极/漏极区，并且与复合栅电极的外边缘自对准。

公开(公告)号：US5763922A

公开(公告)日：1998-06-09

申请号：US810682

申请日：1997-02-28

申请人： Robert S. Chau

发明人： Robert S. Chau

IPC分类号： H01L21/8238 ,  H01L27/092 ,  H01L29/76 ,  H01L29/94

CPC分类号： H01L27/0922 ,  H01L21/823857

摘要： A CMOS integrated circuit having a PMOS and NMOS device with different gate dielectric layers. According to the present invention, an NMOS transistor is formed on a p-type conductivity region of a semiconductor substrate. The NMOS transistor has first gate dielectric layer formed on the p-type conductivity region. A PMOS transistor is formed on a n-type conductivity region of the semiconductor substrate. The PMOS transistor has a second gate dielectric layer wherein the second gate dielectric layer has a different composition than the first gate dielectric layer.

公开(公告)号：US5434093A

公开(公告)日：1995-07-18

申请号：US288332

申请日：1994-08-10

申请人： Robert S. Chau ,  Chan-Hong Chern ,  Shahriar S. Ahmed ,  Robert F. Hainsey ,  Robert J. Stoner ,  Todd E. Wilke ,  Leopoldo D. Yau

发明人： Robert S. Chau ,  Chan-Hong Chern ,  Shahriar S. Ahmed ,  Robert F. Hainsey ,  Robert J. Stoner ,  Todd E. Wilke ,  Leopoldo D. Yau

IPC分类号： H01L21/336 ,  H01L29/08 ,  H01L29/10 ,  H01L29/423 ,  H01L21/265

CPC分类号： H01L29/66583 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/41783 ,  H01L29/42376 ,  H01L29/66553 ,  H01L29/66628 ,  H01L29/66537

摘要： A method for forming narrow length transistors by forming a trench in a first layer over a semiconductor substrate. Spacers are then formed within the trench and a gate dielectric is formed between the spacers at the bottom of the trench on the semiconductor substrate. The trench is then filled with a gate electrode material which is chemically-mechanically polished back to isolate the gate electrode material within the trench, and the first layer is removed leaving the gate dielectric, gate electrode and spacers behind.

摘要翻译： 一种通过在半导体衬底上的第一层中形成沟槽来形成窄长度晶体管的方法。 然后在沟槽内形成间隔物，并且在半导体衬底上的沟槽的底部的间隔物之间​​形成栅极电介质。 然后用栅极电极材料填充沟槽，该栅电极材料被化学机械地抛光以隔离沟槽内的栅极电极材料，并且去除第一层，留下栅极电介质，栅极电极和间隔物。

公开(公告)号：US09634007B2

公开(公告)日：2017-04-25

申请号：US14302350

申请日：2014-06-11

申请人： Ravi Pillarisetty ,  Seung Hoon Sung ,  Niti Goel ,  Jack T. Kavalieros ,  Sansaptak Dasgupta ,  Van H. Le ,  Willy Rachmady ,  Marko Radosavljevic ,  Gilbert Dewey ,  Han Wui Then ,  Niloy Mukherjee ,  Matthew V. Metz ,  Robert S. Chau

发明人： Ravi Pillarisetty ,  Seung Hoon Sung ,  Niti Goel ,  Jack T. Kavalieros ,  Sansaptak Dasgupta ,  Van H. Le ,  Willy Rachmady ,  Marko Radosavljevic ,  Gilbert Dewey ,  Han Wui Then ,  Niloy Mukherjee ,  Matthew V. Metz ,  Robert S. Chau

IPC分类号： H01L29/66 ,  H01L29/78 ,  H01L21/02 ,  H01L21/762 ,  H01L27/092 ,  H01L21/8258 ,  H01L29/423 ,  H01L29/786 ,  B82Y10/00 ,  B82Y40/00 ,  H01L29/775 ,  H01L29/06 ,  H01L21/8238

CPC分类号： H01L21/845 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/02639 ,  H01L21/823807 ,  H01L21/8258 ,  H01L27/092 ,  H01L27/1211 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/6653 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/775 ,  H01L29/78 ,  H01L29/785 ,  H01L29/7853 ,  H01L29/78696

摘要： Trench-confined selective epitaxial growth process in which epitaxial growth of a semiconductor device layer proceeds within the confines of a trench. In embodiments, a trench is fabricated to include a pristine, planar semiconductor seeding surface disposed at the bottom of the trench. Semiconductor regions around the seeding surface may be recessed relative to the seeding surface with Isolation dielectric disposed there on to surround the semiconductor seeding layer and form the trench. In embodiments to form the trench, a sacrificial hardmask fin may be covered in dielectric which is then planarized to expose the hardmask fin, which is then removed to expose the seeding surface. A semiconductor device layer is formed from the seeding surface through selective heteroepitaxy. In embodiments, non-planar devices are formed from the semiconductor device layer by recessing a top surface of the isolation dielectric. In embodiments, non-planar devices CMOS devices having high carrier mobility may be made from the semiconductor device layer.

公开(公告)号：US20160365435A1

公开(公告)日：2016-12-15

申请号：US15120732

申请日：2014-03-25

申请人： Han Wui Then ,  Sansaptak Dasgupta ,  Marko Radosavljevic ,  Robert S. Chau

发明人： Han Wui Then ,  Sansaptak Dasgupta ,  Marko Radosavljevic ,  Robert S. Chau

IPC分类号： H01L29/778 ,  H01L29/20 ,  H01L29/423 ,  H01L29/08

CPC分类号： H01L29/7786 ,  H01L29/045 ,  H01L29/0847 ,  H01L29/2003 ,  H01L29/4236 ,  H01L29/66431 ,  H01L29/66446 ,  H01L29/66462 ,  H01L29/778 ,  H01L29/7783 ,  H01L29/7787

摘要： III-N transistors with epitaxial semiconductor heterostructures having steep subthreshold slope are described. In embodiments, a III-N HFET employs a gate stack with balanced and opposing III-N polarization materials. Overall effective polarization of the opposing III-N polarization materials may be modulated by an external field, for example associated with an applied gate electrode voltage. In embodiments, polarization strength differences between the III-N materials within the gate stack are tuned by composition and/or film thickness to achieve a desired transistor threshold voltage (Vt). With polarization strengths within the gate stack balanced and opposing each other, both forward and reverse gate voltage sweeps may generate a steep sub-threshold swing in drain current as charge carriers are transferred to and from the III-N polarization layers and the III-N channel semiconductor.

摘要翻译： 描述具有陡峭亚阈值斜率的外延半导体异质结构的III-N晶体管。 在实施例中，III-NHFET采用具有平衡和相对的III-N极化材料的栅极叠层。 相对的III-N偏振材料的总体有效极化可以通过外部场来调制，例如与施加的栅电极电压相关联。 在实施例中，栅堆叠内的III-N材料之间的极化强度差异通过组合和/或膜厚来调节以实现期望的晶体管阈值电压（Vt）。 由于栅极堆叠内的极化强度平衡和相互对置，正向和反向栅极电压扫描都可能在漏极电流中产生陡峭的次阈值摆幅，因为电荷载流子传输到III-N偏振层和III-N极化层 通道半导体。

公开(公告)号：US09356099B2

公开(公告)日：2016-05-31

申请号：US14334636

申请日：2014-07-17

申请人： Ravi Pillarisetty ,  Benjamin Chu-Kung ,  Mantu K. Hudait ,  Marko Radosavljevic ,  Jack T. Kavalieros ,  Willy Rachmady ,  Niloy Mukherjee ,  Robert S. Chau

发明人： Ravi Pillarisetty ,  Benjamin Chu-Kung ,  Mantu K. Hudait ,  Marko Radosavljevic ,  Jack T. Kavalieros ,  Willy Rachmady ,  Niloy Mukherjee ,  Robert S. Chau

IPC分类号： H01L29/15 ,  H01L29/41 ,  H01L29/78 ,  H01L29/66 ,  H01L29/778 ,  H01L29/775 ,  H01L29/417 ,  H01L29/423 ,  H01L29/51

CPC分类号： H01L29/7784 ,  H01L29/151 ,  H01L29/155 ,  H01L29/201 ,  H01L29/205 ,  H01L29/401 ,  H01L29/41725 ,  H01L29/41775 ,  H01L29/42316 ,  H01L29/4236 ,  H01L29/517 ,  H01L29/66462 ,  H01L29/775 ,  H01L29/7783 ,  H01L29/78

摘要： Techniques are disclosed for providing a low resistance self-aligned contacts to devices formed in a semiconductor heterostructure. The techniques can be used, for example, for forming contacts to the gate, source and drain regions of a quantum well transistor fabricated in III-V and SiGe/Ge material systems. Unlike conventional contact process flows which result in a relatively large space between the source/drain contacts to gate, the resulting source and drain contacts provided by the techniques described herein are self-aligned, in that each contact is aligned to the gate electrode and isolated therefrom via spacer material.

公开(公告)号：US20150091067A1

公开(公告)日：2015-04-02

申请号：US14040574

申请日：2013-09-27

申请人： Ravi Pillarisetty ,  Brian S. Doyle ,  Elijah V. Karpov ,  David L. Kencke ,  Uday Shah ,  Charles C. Kuo ,  Robert S. Chau

发明人： Ravi Pillarisetty ,  Brian S. Doyle ,  Elijah V. Karpov ,  David L. Kencke ,  Uday Shah ,  Charles C. Kuo ,  Robert S. Chau

IPC分类号： H01L29/78 ,  H01L29/66

CPC分类号： H01L27/2436 ,  H01L29/66477 ,  H01L29/66568 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/785 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1616 ,  H01L2029/7858

摘要： An insulating layer is deposited over a transistor structure. The transistor structure comprises a gate electrode over a device layer on a substrate. The transistor structure comprises a first contact region and a second contact region on the device layer at opposite sides of the gate electrode. A trench is formed in the first insulating layer over the first contact region. A metal-insulator phase transition material layer with a S-shaped IV characteristic is deposited in the trench or in the via of the metallization layer above on the source side.

摘要翻译： 在晶体管结构上沉积绝缘层。 晶体管结构包括位于衬底上的器件层上的栅电极。 晶体管结构包括在栅电极的相对侧的器件层上的第一接触区域和第二接触区域。 在第一接触区域上的第一绝缘层中形成沟槽。 具有S形IV特性的金属 - 绝缘体相变材料层沉积在源极侧上方的金属化层的沟槽或通路中。

公开(公告)号：US20140374689A1

公开(公告)日：2014-12-25

申请号：US13925951

申请日：2013-06-25

申请人： Elijah V. Karpov ,  Brian S. Doyle ,  Uday Shah ,  Robert S. Chau

发明人： Elijah V. Karpov ,  Brian S. Doyle ,  Uday Shah ,  Robert S. Chau

IPC分类号： H01L45/00 ,  H01L27/24

CPC分类号： H01L45/146 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/1266

摘要： Conductive oxide random access memory (CORAM) cells and methods of fabricating CORAM cells are described. For example, a material layer stack for a memory element includes a first conductive electrode. An insulating layer is disposed on the first conductive oxide and has an opening with sidewalls therein that exposes a portion of the first conductive electrode. A conductive oxide layer is disposed in the opening, on the first conductive electrode and along the sidewalls of the opening. A second electrode is disposed in the opening, on the conductive oxide layer.

摘要翻译： 描述了导电氧化物随机存取存储器（CORAM）单元和制造CORAM单元的方法。 例如，用于存储元件的材料层堆叠包括第一导电电极。 绝缘层设置在第一导电氧化物上并且具有露出第一导电电极的一部分的侧壁的开口。 导电氧化物层设置在开口中，在第一导电电极上并且沿着开口的侧壁。 第二电极设置在开口中，在导电氧化物层上。