公开(公告)号：US09679627B2

公开(公告)日：2017-06-13

申请号：US14502367

申请日：2014-09-30

Applicant: Everspin Technologies, Inc.

Inventor： Thomas Andre ,  Dimitri Houssameddine ,  Syed M. Alam ,  Jon Slaughter ,  Chitra Subramanian

IPC: G11C16/04 ,  G11C11/16 ,  G06F12/0804

CPC classification number: G11C11/1675 ,  G06F12/0804 ,  G11C11/1677 ,  Y02D10/13

Abstract: A memory device is configured to identify a set of bit cells to be changed from a first state to a second state. In some examples, the memory device may apply a first voltage to the set of bit cells to change a least a first portion of the set of bit cells to the second state. In some cases, the memory device may also identify a second portion of the bit cells that remained in the first state following the application of the first voltage. In these cases, the memory device may apply a second voltage having a greater magnitude, duration, or both to the second portion of the set of bit cells in order to set the second portion of bit cells to the second state.

公开(公告)号：US20170092347A1

公开(公告)日：2017-03-30

申请号：US15369246

申请日：2016-12-05

Applicant: Everspin Technologies, Inc.

Inventor： Dietmar Gogl ,  Syed M. Alam ,  Thomas Andre

IPC: G11C11/16

CPC classification number: G11C11/1675 ,  G11C5/147 ,  G11C11/161 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1697 ,  G11C13/0069 ,  G11C2213/79

Abstract: A cell bias control circuit maximizes the performance of devices in the read/write path of memory cells (magnetic tunnel junction device+transistor) without exceeding leakage current or reliability limits by automatically adjusting multiple control inputs of the read/write path at the memory array according to predefined profiles over supply voltage, temperature, and process corner variations by applying any specific reference parameter profiles to the memory array.

公开(公告)号：US09583169B2

公开(公告)日：2017-02-28

申请号：US15149401

申请日：2016-05-09

Applicant: Everspin Technologies, Inc.

Inventor： Dietmar Gogl ,  Syed M. Alam ,  Thomas Andre ,  Halbert S. Lin

IPC: G11C11/00 ,  G11C11/16 ,  G11C8/08

CPC classification number: G11C11/1673 ,  G11C8/08 ,  G11C11/1657 ,  G11C11/1693 ,  G11C11/1697

Abstract: A boosted supply voltage generator is selectively activated and deactivated to allow operations that are sensitive to variations on the boosted voltage to be performed with a stable boosted voltage. Techniques for deactivating and reactivating the voltage generator are also disclosed that enable more rapid recovery from deactivation such that subsequent operations can be commenced sooner. Such techniques include storing state information corresponding to the voltage generator when deactivated, where the stored state information is used when reactivating the voltage generator. Stored state information can include a state of a clock signal provided to the voltage generator.

Abstract translation: 升压的电源电压发生器被选择性地激活和去激活，以允许以稳定的升压电压来执行对升压电压的变化敏感的操作。 还公开了用于停用和重新激活电压发生器的技术，其使得能够从停用中更快速地恢复，使得可以更快地开始后续操作。 这样的技术包括当停用时存储对应于电压发生器的状态信息，其中在重新激活电压发生器时使用存储的状态信息。 存储状态信息可以包括提供给电压发生器的时钟信号的状态。

公开(公告)号：US09575125B1

公开(公告)日：2017-02-21

申请号：US14049543

申请日：2013-10-09

Applicant: Everspin Technologies, Inc.

Inventor： Thomas Andre ,  Syed M. Alam ,  William Meadows

IPC: G01R31/3193 ,  G11C29/10

CPC classification number: G01R31/3193 ,  G01R31/31718 ,  G11C29/10 ,  G11C29/42 ,  G11C29/52

Abstract: In some examples, a memory device generates and exposes parity/difference information to a test system to reduce overall test time. The parity/difference information may be generated based on parity bits read from the memory device and parity bits produced from data bits stored in the memory device. In some cases, the parity/difference information may be compared to an expected parity/difference to determine a number of correctable errors which occurred during testing, while the data bits may be compared to expected data to determine a number of uncorrectable errors which occurred during testing.

Abstract translation: 在一些示例中，存储器件生成并将奇偶校验/差异信息暴露给测试系统以减少总体测试时间。 可以基于从存储器件读取的奇偶校验位和从存储在存储器件中的数据位产生的校验位来生成校验/差分信息。 在某些情况下，可以将奇偶校验/差分信息与期望的奇偶校验/差异进行比较，以确定在测试期间发生的可校正错误的数量，同时可将数据比特与期望数据进行比较，以确定在期间发生的不可校正错误的数量 测试。

公开(公告)号：US09552863B1

公开(公告)日：2017-01-24

申请号：US14872438

申请日：2015-10-01

Applicant: Everspin Technologies, Inc.

Inventor： Thomas Andre ,  Syed Alam ,  Chitra K. Subramanian ,  Dietmar Gogl

IPC: G11C11/00 ,  G11C11/16 ,  G11C13/00 ,  G11C11/14 ,  G11C11/15

CPC classification number: G11C11/1675 ,  G11C11/14 ,  G11C11/15 ,  G11C11/16 ,  G11C11/1677 ,  G11C13/0002 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2013/0076 ,  G11C2013/0088

Abstract: A memory device is configured to identify a set of bit cells to be changed from a first state to a second state. In some examples, the memory device may apply a first voltage to the set of bit cells to change a least a first portion of the set of bit cells to the second state. In some cases, the memory device may also identify a second portion of the bit cells that remained in the first state following the application of the first voltage. In these cases, the memory device may apply a second voltage having a greater magnitude, duration, or both to the second portion of the set of bit cells in order to set the second portion of bit cells to the second state.

Abstract translation: 存储器设备被配置为识别要从第一状态改变到第二状态的位单元的集合。 在一些示例中，存储器件可以向该位单元集合施加第一电压以将位组中的至少第一部分改变为第二状态。 在一些情况下，存储器件还可以识别在应用第一电压之后保持在第一状态的位单元的第二部分。 在这些情况下，存储器件可以将具有更大幅度，持续时间或两者的第二电压施加到位单元集合的第二部分，以便将位单元的第二部分设置为第二状态。

公开(公告)号：US09529726B2

公开(公告)日：2016-12-27

申请号：US14155816

申请日：2014-01-15

Applicant: EVERSPIN TECHNOLOGIES, INC.

Inventor： Syed M. Alam ,  Thomas Andre

IPC: G06F12/08

CPC classification number: G06F11/1096 ,  G06F11/1064 ,  G06F12/0882 ,  G06F2211/109 ,  G06F2212/652 ,  G11C14/0036

Abstract: In some examples, a memory device is configured to load multiple pages of an internal page size into a cache in response to receiving an activate command and to write multiple pages of the internal page size into a memory array in response to receiving a precharge command. In some implementations, the memory array is arranged to store multiple pages of the internal page size in a single physical row.

Abstract translation: 在一些示例中，存储器设备被配置为响应于接收到激活命令而将内部页面大小的页面加载到高速缓存中，并且响应于接收到预充电命令而将内部页面大小的多页写入存储器阵列。 在一些实现中，存储器阵列被布置成在单个物理行中存储内部页面大小的多个页面。

公开(公告)号：US20160307615A1

公开(公告)日：2016-10-20

申请号：US15193010

申请日：2016-06-25

Applicant: Everspin Technologies, Inc.

Inventor： Thomas Andre ,  Syed M. Alam ,  Chitra Subramanian

IPC: G11C11/16

CPC classification number: G11C11/1675 ,  G11C7/02 ,  G11C7/065 ,  G11C11/16 ,  G11C11/1655 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1693 ,  G11C2013/0057 ,  G11C2207/002

Abstract: Self-referenced reading of a memory cell in a memory includes first applying a read voltage across the memory cell to produce a sample voltage. After applying the read voltage, a write current is applied to the memory cell to write a first state to the memory cell. After applying the write current, the read voltage is reapplied across the memory cell. An offset current is also applied while the read voltage is reapplied, and the resulting evaluation voltage from reapplying the read voltage with the offset current is compared with the sample voltage to determine the state of the memory cell.

Abstract translation: 存储器单元的自参考读取包括首先在存储器单元上施加读取电压以产生采样电压。 在施加读取电压之后，将写入电流施加到存储器单元以将第一状态写入存储单元。 在施加写入电流之后，读取电压被重新应用于存储器单元。 在重新施加读取电压的同时施加偏置电流，并将得到的评估电压与读取电压重新应用偏移电流相比较，以确定存储单元的状态。

公开(公告)号：US20160254040A1

公开(公告)日：2016-09-01

申请号：US15149401

申请日：2016-05-09

Applicant: Everspin Technologies, Inc.

Inventor： Dietmar Gogl ,  Syed M. Alam ,  Thomas Andre ,  Halbert S. Lin

IPC: G11C11/16

CPC classification number: G11C11/1673 ,  G11C8/08 ,  G11C11/1657 ,  G11C11/1693 ,  G11C11/1697

Abstract: A boosted supply voltage generator is selectively activated and deactivated to allow operations that are sensitive to variations on the boosted voltage to be performed with a stable boosted voltage. Techniques for deactivating and reactivating the voltage generator are also disclosed that enable more rapid recovery from deactivation such that subsequent operations can be commenced sooner. Such techniques include storing state information corresponding to the voltage generator when deactivated, where the stored state information is used when reactivating the voltage generator. Stored state information can include a state of a clock signal provided to the voltage generator.

Abstract translation: 升压的电源电压发生器被选择性地激活和去激活，以允许以稳定的升压电压来执行对升压电压的变化敏感的操作。 还公开了用于停用和重新激活电压发生器的技术，其使得能够从停用中更快速地恢复，使得可以更快地开始后续操作。 这样的技术包括当停用时存储对应于电压发生器的状态信息，其中在重新激活电压发生器时使用存储的状态信息。 存储状态信息可以包括提供给电压发生器的时钟信号的状态。

公开(公告)号：US09412786B1

公开(公告)日：2016-08-09

申请号：US14872708

申请日：2015-10-01

Applicant: Everspin Technologies, Inc.

Inventor： Thomas Andre ,  Sanjeev Aggarwal ,  Kerry Joseph Nagel ,  Sarin A. Deshpande

IPC: H01L29/82 ,  H01L43/00 ,  H01L27/22 ,  H01L43/02 ,  H01L43/08 ,  G11C11/16 ,  H01L23/522

CPC classification number: H01L27/222 ,  G11C11/161 ,  H01L43/08 ,  H01L43/12

Abstract: Magnetoresistive device architectures and methods for manufacturing are presented that facilitate integration of process steps associated with forming such devices into standard process flows used for surrounding logic/circuitry. In some embodiments, the magnetoresistive device structures are designed such that the devices are able to fit within the vertical dimensions of the integrated circuit associated with a single metal layer and a single layer of interlayer dielectric material. Integrating the processing for the magnetoresistive devices can include using the same standard interlayer dielectric material as used in the surrounding circuits on the integrated circuit as well as using standard vias to interconnect to at least one of the electrodes of the magnetoresistive devices.

Abstract translation: 提出了磁阻器件结构和制造方法，其有助于将与将这些器件形成相关联的工艺步骤集成到用于周围逻辑/电路的标准工艺流程中。 在一些实施例中，磁阻器件结构被设计成使得器件能够安装在与单个金属层和单层层间电介质材料相关联的集成电路的垂直尺寸内。 集成用于磁阻器件的处理可以包括使用与在集成电路上的周围电路中使用的相同的标准层间绝缘材料，以及使用标准通孔来互连到磁阻器件的至少一个电极。

公开(公告)号：US09311980B1

公开(公告)日：2016-04-12

申请号：US14052223

申请日：2013-10-11

Applicant: Everspin Technologies, Inc.

Inventor： Dietmar Gogl ,  Syed M. Alam ,  Thomas Andre ,  Halbert S. Lin

IPC: G11C11/00 ,  G11C11/16

CPC classification number: G11C11/1673 ,  G11C8/08 ,  G11C11/1657 ,  G11C11/1693 ,  G11C11/1697

Abstract: A word line supply voltage generator is selectively activated and deactivated to allow internal memory operations that are sensitive to variations on word line voltages to be performed with a stable word line voltage. Techniques for deactivating and reactivating the voltage generator are also disclosed that enable more rapid recovery from deactivation such that subsequent operations can be commenced sooner.

Abstract translation: 字线电源电压发生器被选择性地激活和去激活以允许以稳定的字线电压执行对字线电压变化敏感的内部存储器操作。 还公开了用于停用和重新激活电压发生器的技术，其使得能够从停用中更快速地恢复，使得可以更快地开始后续操作。