公开(公告)号：US10050118B2

公开(公告)日：2018-08-14

申请号：US14269566

申请日：2014-05-05

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Ryan Ryoung-han Kim ,  Chanro Park ,  William James Taylor, Jr. ,  John A. Iacoponi

IPC: H01L29/66 ,  H01L21/336 ,  H01L29/06 ,  H01L29/78

Abstract: In one aspect a semiconductor device as set forth herein can include a spacer having a first section of a first material and a second section of a second material, the second section disposed above a certain elevation and the first section disposed below the certain elevation. In one aspect a semiconductor device as set forth herein can include a conductive gate structure having a first length at elevations below a certain elevation and a second length at elevations above the certain elevation, the second length being less than the first length. A semiconductor device having one or more of a plural material spacer or a reduced length upper elevation conductive gate structure can feature a reduced likelihood of electrical shorting.

公开(公告)号：US20180122919A1

公开(公告)日：2018-05-03

申请号：US15337254

申请日：2016-10-28

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Chanro Park ,  Ruilong Xie ,  Hoon Kim ,  Min Gyu Sung

IPC: H01L29/66 ,  H01L29/40 ,  H01L21/28 ,  H01L21/3213

CPC classification number: H01L29/66545 ,  H01L21/28026 ,  H01L21/3213 ,  H01L29/401 ,  H01L29/66568 ,  H01L29/66636 ,  H01L29/66795

Abstract: One illustrative method disclosed includes, among other things, removing a portion of an initial gate cap layer and a portion of an initial sidewall spacer so as to thereby define a gate contact cavity that exposes a portion of a gate structure, completely forming a conductive gate contact structure (CB) in a gate contact cavity, wherein the entire conductive gate contact structure (CB) is positioned vertically above the active region. The method also comprises removing the remaining portion of the initial gate cap layer and to recess a vertical height of exposed portions of the initial sidewall spacer to thereby define a recessed sidewall spacer and a gate cap cavity and forming a replacement gate cap layer in the gate cap cavity so as to define an air space between an upper surface of the recessed sidewall spacer and a lower surface of the replacement gate cap layer.

公开(公告)号：US20180033871A1

公开(公告)日：2018-02-01

申请号：US15219403

申请日：2016-07-26

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Chanro Park ,  Min Gyu Sung ,  Hoon Kim

IPC: H01L29/66 ,  H01L21/308 ,  H01L21/02 ,  H01L29/06 ,  H01L29/165

CPC classification number: H01L29/66545 ,  H01L21/02532 ,  H01L21/3086 ,  H01L29/0673 ,  H01L29/165 ,  H01L29/66795

Abstract: One illustrative method disclosed herein includes, among other things, forming channel semiconductor material for a nano-sheet device and a transistor device, forming a device gate insulation layer on both the nano-sheet device and on the transistor device, and forming first and second sacrificial gate structures for the nano-sheet device and the transistor device. In this example, the method also includes removing the sacrificial gate structures so as to define, respectively, first and second gate cavities, wherein the device gate insulation layer is exposed within each of the gate cavities, removing the device gate insulation layer for the transistor device from within the first gate cavity while leaving the device gate insulation layer in position within the second gate cavity, and forming first and second replacement gate structures in the first and second gate cavities, respectively.

公开(公告)号：US09847390B1

公开(公告)日：2017-12-19

申请号：US15434205

申请日：2017-02-16

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ruilong Xie ,  Chanro Park ,  Min Gyu Sung ,  Hoon Kim

IPC: H01L21/00 ,  H01L29/06 ,  H01L29/417 ,  H01L29/08 ,  H01L29/423 ,  H01L21/02 ,  H01L29/161 ,  H01L29/786 ,  H01L29/66 ,  H01L29/45

CPC classification number: H01L29/0673 ,  H01L21/02532 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/41733 ,  H01L29/41783 ,  H01L29/42392 ,  H01L29/45 ,  H01L29/665 ,  H01L29/66742 ,  H01L29/78684

Abstract: This disclosure relates to forming a wrap-around contact on a nanosheet transistor, the method including: forming an etch-stop layer over a continuous outer surface of a raised source/drain (S/D) region of the nanosheet transistor; forming a sacrificial layer over the etch-stop layer, the etch-stop layer including a different material than the sacrificial layer; depositing a dielectric layer over the sacrificial layer; removing an upper portion of the dielectric layer to expose a portion of the sacrificial layer; removing the sacrificial layer selective to the etch-stop layer; and depositing a conductor in the removed upper portion of the dielectric layer to form a wrap-around contact and a second contact.

公开(公告)号：US09837404B2

公开(公告)日：2017-12-05

申请号：US15082242

申请日：2016-03-28

Applicant: GLOBALFOUNDRIES INC.

Inventor： Min Gyu Sung ,  Chanro Park ,  Hoon Kim ,  Ruilong Xie ,  Kwan-Yong Lim

IPC: H01L21/336 ,  H01L29/66 ,  H01L29/78 ,  H01L21/308 ,  H01L21/8234 ,  H01L27/088 ,  H01L21/3105 ,  H01L21/311

CPC classification number: H01L27/0886 ,  H01L21/31053 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/823431 ,  H01L21/823481 ,  H01L21/823821 ,  H01L21/845 ,  H01L29/66795 ,  H01L29/785

Abstract: At least one method, apparatus and system are disclosed for forming a fin field effect transistor (finFET) having an oxide level in a fin array region within a predetermined height of the oxide level of a field region. A first oxide process is performed for controlling a first oxide recess level in a field region adjacent to a fin array region comprising a plurality of fins in a finFET device. The first oxide process comprises depositing an oxide layer over the field region and the fin array region and performing an oxide recess process to bring the oxide layer to the first oxide recess level in the field region. A second oxide process is performed for controlling a second oxide recess level in the fin array region. The second oxide process comprises isolating the fin array region, depositing oxide material, and performing an oxide recess process to bring the oxide level in the fin array region to the second oxide recess level. The first oxide recess level is within a predetermined height differential of the second oxide recess level.

公开(公告)号：US09818836B1

公开(公告)日：2017-11-14

申请号：US15486387

申请日：2017-04-13

Applicant: GLOBALFOUNDRIES INC.

Inventor： Min Gyu Sung ,  Ruilong Xie ,  Chanro Park ,  Dong-Ick Lee

IPC: H01L29/51 ,  H01L29/66

CPC classification number: H01L29/513 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: A method of manufacturing a FinFET structure involves forming a gate cut within a sacrificial gate layer and backfilling the gate cut opening with etch selective dielectric materials. Partial etching of one of the dielectric materials can be used to increase the distance between the gate cut (isolation) structure and an adjacent fin relative to methods that do not perform a backfilling step using etch selective materials.

公开(公告)号：US20170309714A1

公开(公告)日：2017-10-26

申请号：US15639095

申请日：2017-06-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Chanro Park ,  Min Gyu Sung ,  Hoon Kim

IPC: H01L29/41 ,  H01L29/417 ,  H01L29/08 ,  H01L29/06 ,  H01L27/088 ,  H01L29/45 ,  H01L27/02

CPC classification number: H01L29/41775 ,  H01L27/0207 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/41 ,  H01L29/41766 ,  H01L29/41783 ,  H01L29/41791 ,  H01L29/45 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: One illustrative method disclosed includes, among other things, forming an initial conductive source/drain structure that is conductively coupled to a source/drain region of a transistor device, performing a recess etching process on the initial conductive source/drain structure to thereby define a stepped conductive source/drain structure with a cavity defined therein, forming a non-conductive structure in the cavity, forming a layer of insulating material above the gate structure, the stepped conductive source/drain structure and the non-conductive structure, forming a gate contact opening in the layer of insulating material and forming a conductive gate contact in the gate contact opening that is conductively coupled to the gate structure.

公开(公告)号：US09799748B1

公开(公告)日：2017-10-24

申请号：US15398335

申请日：2017-01-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Min Gyu Sung ,  Chanro Park ,  Hoon Kim

IPC: H01L21/00 ,  H01L29/66 ,  H01L21/306 ,  H01L21/308

CPC classification number: H01L21/3085 ,  H01L21/30604 ,  H01L29/0673 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66795

Abstract: A method includes forming a stack of semiconductor material layers above a substrate. The stack includes at least one first semiconductor material layer and at least one second semiconductor material layer. A first etching process is performed on the stack to define cavities. The cavities expose end portions of the first and second semiconductor material layers. Portions of the first semiconductor material layer are removed to define end recesses. A layer of insulating material is formed in the end recesses and at least partially fills the cavities. A second etching process is performed on the stack to remove end portions of the at least one second semiconductor material layer and to remove portions of the layer of insulating material in the cavities not disposed between the first and second semiconductor material layers so as to form inner spacers on ends of the at least one first semiconductor material layer.

公开(公告)号：US20170294338A1

公开(公告)日：2017-10-12

申请号：US15630546

申请日：2017-06-22

Applicant: GLOBALFOUNDRIES INC.

Inventor： Min Gyu Sung ,  Ruilong Xie ,  Hoon Kim ,  Chanro Park ,  Sukwon Hong

IPC: H01L21/762 ,  H01L21/311 ,  H01L21/02

CPC classification number: H01L21/76224 ,  H01L21/02271 ,  H01L21/02337 ,  H01L21/31111 ,  H01L21/31116 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/1037 ,  H01L29/16 ,  H01L29/161 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/785

Abstract: At least one method, apparatus and system are disclosed for forming a fin field effect transistor (finFET) while reducing oxidization and fin critical dimension loss. A plurality of fins of a transistor are formed. A hard mask layer is formed on top of the fins. A first liner layer is formed over the fins and the hard mask layer. A partial deposition process is performed for depositing a first insulation material in a first portion of a channel between the fins. A second liner layer is formed above the fins, the first insulation material, and the channel. A second insulation material is deposited above the second liner layer. A fin reveal process is performed for removing the second insulation material to a predetermined height. An etch process is performed for removing the hard mask layer and the first and second liner layers above the predetermined height.

公开(公告)号：US09780208B1

公开(公告)日：2017-10-03

申请号：US15212755

申请日：2016-07-18

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Chanro Park ,  Min Gyu Sung ,  Hoon Kim

IPC: H01L29/51 ,  H01L29/78 ,  H01L29/66 ,  H01L29/08 ,  H01L21/324 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/49 ,  H01L21/28

CPC classification number: H01L29/7827 ,  H01L21/28088 ,  H01L21/324 ,  H01L21/823418 ,  H01L21/823437 ,  H01L21/823487 ,  H01L27/088 ,  H01L29/0847 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66666

Abstract: An intermediate semiconductor structure in fabrication includes a silicon semiconductor substrate, a hard mask of silicon nitride (SiN) over the substrate and a sacrificial layer of polysilicon or amorphous silicon over the hard mask. The sacrificial layer is patterned into sidewall spacers, each of the sidewall spacers having vertically tapered inner and outer sidewalls providing a rough triangular shape. The rough triangular sidewall spacers are used as a temporary hard mask to pattern the SiN hard mask.