公开(公告)号：US09899321B1

公开(公告)日：2018-02-20

申请号：US15373691

申请日：2016-12-09

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Chanro Park ,  Ruilong Xie ,  Min Gyu Sung ,  Hoon Kim

IPC: H01L21/28 ,  H01L23/528 ,  H01L23/522 ,  H01L21/768 ,  H01L29/66 ,  H01L29/417

CPC classification number: H01L23/528 ,  H01L21/28 ,  H01L21/28114 ,  H01L21/28123 ,  H01L21/7684 ,  H01L23/5226 ,  H01L29/41775 ,  H01L29/66553

Abstract: One illustrative method disclosed includes, among other things, completely forming a first conductive structure comprising one of a conductive gate contact structure (CB) or a conductive source/drain contact structure (CA), wherein the entire conductive gate contact structure (CB) is positioned vertically above a portion of an active region of a transistor device, and, after completely forming the first conductive structure, completely forming a second conductive structure comprising the other of the conductive gate contact structure (CB) or the conductive source/drain contact structure (CA).

公开(公告)号：US20180047564A1

公开(公告)日：2018-02-15

申请号：US15233445

申请日：2016-08-10

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Chanro Park ,  Hoon Kim ,  Min Gyu Sung ,  Ruilong Xie

IPC: H01L21/027 ,  H01L21/306 ,  H01L21/263

CPC classification number: H01L21/263 ,  H01L21/0338 ,  H01L21/31122 ,  H01L21/31144

Abstract: A novel method of processing and fabricating semiconductor devices is provided to reduce critical dimensions inherent in a given photolithography process. A patterned mask layer generated via transfer of the pattern to the masking layer (e.g., printing) has a given set of dimensions. The method or process forms multiple layers beneath a masking layer. The multiple layers are etched to form openings therein according to the original mask pattern. Thereafter, one of the multiple layers is etched along its sidewalls to increase the opening therethrough, and this layer is utilized as the mask layer for the underlying semiconductor substrate. This enables a reduction in the critical dimensions, at least a critical dimension related to spacing between two features.

公开(公告)号：US20180033863A1

公开(公告)日：2018-02-01

申请号：US15225152

申请日：2016-08-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Min Gyu Sung ,  Chanro Park ,  Hoon Kim

IPC: H01L29/49 ,  H01L21/768 ,  H01L29/40 ,  H01L23/535 ,  H01L29/06

CPC classification number: H01L29/4991 ,  H01L21/764 ,  H01L21/76805 ,  H01L21/7682 ,  H01L21/76897 ,  H01L23/535 ,  H01L29/0653 ,  H01L29/401 ,  H01L29/66795 ,  H01L29/785

Abstract: One illustrative method disclosed herein includes, among other things, forming a gate structure above an active region and an isolation region, wherein the gate structure comprises a gate, a first gate cap layer and a first sidewall spacer, removing portions of the first gate cap layer and the first sidewall spacer that are positioned above the active region, while leaving portions of the first gate cap layer and the first sidewall spacer positioned above the isolation region in place, wherein a plurality of spacer cavities are defined adjacent the gate, and forming a replacement air-gap spacer in each of the spacer cavities adjacent the gate and a replacement gate cap layer above the gate, wherein the replacement air-gap spacer comprises an air gap.

公开(公告)号：US09847418B1

公开(公告)日：2017-12-19

申请号：US15219917

申请日：2016-07-26

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Kwan-Yong Lim ,  Min Gyu Sung ,  Chanro Park

IPC: H01L21/33 ,  H01L21/20 ,  H01L21/36 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/7848 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66795

Abstract: A method includes forming a fin on a substrate. A first liner is formed on the fin. A first dielectric layer is formed above the first liner. A patterned hard mask is formed above the first dielectric layer and has a fin cut opening defined therein. Portions of the first dielectric layer and the first liner disposed below the fin cut opening are removed to expose a portion of the fin. The patterned hard mask layer is removed. The exposed portion of the fin is oxidized to define a diffusion break in the fin.

公开(公告)号：US20170316985A1

公开(公告)日：2017-11-02

申请号：US15647453

申请日：2017-07-12

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Min Gyu Sung ,  Chanro Park ,  Ruilong Xie ,  Hoon Kim

IPC: H01L21/8238 ,  H01L27/092

CPC classification number: H01L21/823821 ,  H01L21/823807 ,  H01L27/0924

Abstract: An integrated circuit product includes an NFET FinFET device having a first fin that is made entirely of a first semiconductor material and a PFET FinFET device that includes a second fin having an upper portion and a lower portion, wherein the lower portion is made of the first semiconductor material and the upper portion is made of a second semiconductor material that is different from the first semiconductor material. A silicon nitride liner is positioned on and in contact with the lower portion of the second fin, wherein the silicon nitride liner is not present on or adjacent to the upper portion of the second fin or on or adjacent to any portion of the first fin.

公开(公告)号：US20170287780A1

公开(公告)日：2017-10-05

申请号：US15089834

申请日：2016-04-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Chanro Park ,  Ruilong Xie ,  Hoon Kim ,  Min Gyu Sung

IPC: H01L21/768 ,  H01L21/28 ,  H01L23/535 ,  H01L27/092 ,  H01L29/49 ,  H01L21/8238 ,  H01L29/66

CPC classification number: H01L21/76897 ,  H01L21/28088 ,  H01L21/76805 ,  H01L21/76834 ,  H01L21/76883 ,  H01L21/823456 ,  H01L21/823475 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/823871 ,  H01L23/535 ,  H01L27/0924 ,  H01L29/4966 ,  H01L29/66545

Abstract: One method disclosed includes, among other things, forming a first plurality of gate cavities in a first dielectric layer. A work function material layer is formed in the first plurality of gate cavities. A first conductive material is formed in at least a subset of the first plurality of gate cavities above the work function material layer to define a first plurality of gate structures. A first contact recess is formed in the first dielectric layer between two of the first plurality of gate structures. A second conductive material is formed in the first contact recess. The work function material layer is recessed selectively to the first and second conductive materials to define a plurality of cap recesses. A cap layer is formed in the plurality of cap recesses.

公开(公告)号：US09780197B1

公开(公告)日：2017-10-03

申请号：US15378596

申请日：2016-12-14

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ruilong Xie ,  Min Gyu Sung ,  Chanro Park ,  Hoon Kim

IPC: H01L29/66 ,  H01L29/786 ,  H01L29/423 ,  H01L29/51 ,  H01L29/49 ,  H01L21/28

CPC classification number: H01L29/66666 ,  H01L21/28088 ,  H01L29/42392 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66553

Abstract: Methods for making a vertical transistor and controlling channel length. A fin is formed over a semiconductor substrate. A bottom source/drain region is formed below the fin. A bottom spacer is formed above the source/drain region. A first sacrificial layer is formed around the fin. A second sacrificial layer is formed around the first sacrificial layer. A portion of the first sacrificial layer is removed to create a recess between sidewalls of the second sacrificial layer. A nitride material is deposited into the recess. The second sacrificial layer and remaining portions of the first sacrificial layer are removed. A dielectric layer is deposited on the nitride material and exposed portions of the fin. A gate electrode is formed over sidewalls of the fin.

公开(公告)号：US09779960B2

公开(公告)日：2017-10-03

申请号：US14726712

申请日：2015-06-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Min Gyu Sung ,  Catherine B. Labelle

IPC: H01L21/311 ,  B23P15/00 ,  C03C25/00 ,  C23F1/00 ,  H01L21/308

CPC classification number: H01L21/3086 ,  H01L21/3083

Abstract: One illustrative method disclosed herein includes, among other things, forming a fin-removal masking layer comprised of a plurality of line-type features, each of which is positioned above one of the fins, and a masking material positioned at least between adjacent features of the fin-removal masking layer and above portions of an insulating material in the trenches between the fins. The method also includes performing an anisotropic etching process through the fin-removal masking layer to remove the portions of the fins to be removed.

公开(公告)号：US09741623B2

公开(公告)日：2017-08-22

申请号：US14828652

申请日：2015-08-18

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Min Gyu Sung ,  Chanro Park ,  Ruilong Xie ,  Hoon Kim

IPC: H01L21/8238 ,  H01L27/092

CPC classification number: H01L21/823821 ,  H01L21/823807 ,  H01L27/0924

Abstract: One illustrative method disclosed herein includes, among other things, performing a first trench etching process to define an upper portion of a first fin for an NFET device and an upper portion of a second fin for a PFET device, performing a first conformal deposition process to form a conformal etch stop layer around the upper portion of both the first and second fins, with the NFET device masked, performing a second trench etching process to define a lower portion of the second fin, and performing a second conformal deposition process to form a conformal protection layer adjacent the upper portion of the second fin and on sidewalls of the lower portion of the second fin.

公开(公告)号：US09735063B2

公开(公告)日：2017-08-15

申请号：US14830245

申请日：2015-08-19

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Chanro Park ,  Min Gyu Sung ,  Hoon Kim ,  Ruilong Xie

IPC: H01L21/8238 ,  H01L21/02 ,  H01L21/3105 ,  H01L29/66 ,  H01L21/311

CPC classification number: H01L21/823821 ,  H01L21/02112 ,  H01L21/02115 ,  H01L21/0217 ,  H01L21/02271 ,  H01L21/31056 ,  H01L21/31116 ,  H01L21/823807 ,  H01L21/823892 ,  H01L29/66795

Abstract: A method includes providing a substrate having a first and a second plurality of fins with a first at least one dielectric material disposed thereon, removing upper portions of the first dielectric material to expose upper portions of the first and the second plurality of fins, removing the first dielectric material from the lower portions of the second plurality of fins to expose lower portions of the second plurality of fins, depositing a second at least one dielectric material on at least the upper and the lower exposed portions of the second plurality of fins and on the upper exposed portions of first plurality of fins, removing the second dielectric material to expose upper portions of the first and the second plurality of fins, and wherein the first dielectric material is different from the second dielectric material. The resulting structure may be operable for use as nFETs and pFETs.