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    TRACING DATA FROM AN ASYNCHRONOUS INTERFACE
    95.
    发明申请
    TRACING DATA FROM AN ASYNCHRONOUS INTERFACE 有权
    从非同步接口追踪数据

    公开(公告)号：US20150365225A1

    公开(公告)日：2015-12-17

    申请号：US14733249

    申请日：2015-06-08

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Norbert Hagspiel ,  Sascha Junghans ,  Matthias Klein ,  Joerg Walter

    IPC: H04L7/02 ,  H04L7/00

    CPC classification number: G06F11/348 ,  G06F11/3027 ,  G06F11/349 ,  G06F2201/86 ,  H04L7/0045 ,  H04L7/02

    Abstract: An apparatus for tracing data from a data bus in a first clock domain operating at a first clock frequency to a trace array in a second clock domain operating at a second clock frequency, wherein the first clock frequency is lower than the second clock frequency. The apparatus includes a change detector to detect a change of the data on the data bus in the first clock domain, a trigger responsive to the change detector to send a trigger pulse to the second clock domain, pulse synchronization on the second clock domain responsive to the trigger pulse to synchronize the trigger pulse to the second clock frequency of the second clock domain by a meta-stability latch, as well as a data capture in the second clock domain responsive to the pulse synchronization to capture data from the data bus and to store the captured data in the trace array.

    Abstract translation: 一种用于在以第一时钟频率操作的第一时钟域中的数据总线跟踪数据到在第二时钟频率下操作的第二时钟域中的跟踪阵列的装置，其中所述第一时钟频率低于所述第二时钟频率。 该装置包括：变化检测器，用于检测在第一时钟域中的数据总线上的数据的变化;触发响应于变化检测器的触发信号以向第二时钟域发送触发脉冲，响应于第二时钟域的脉冲同步 所述触发脉冲通过元稳定性锁存器将所述触发脉冲与所述第二时钟域的所述第二时钟频率同步，以及响应于所述脉冲同步以从所述数据总线捕获数据的所述第二时钟域中的数据捕获，以及 将捕获的数据存储在跟踪数组中。

    Input/output traffic backpressure prediction
    96.
    发明授权
    Input/output traffic backpressure prediction 有权
    输入/输出业务背压预测

    公开(公告)号：US09183042B2

    公开(公告)日：2015-11-10

    申请号：US14077156

    申请日：2013-11-11

    Applicant: International Business Machines Corporation

    Inventor： Norbert Hagspiel ,  Matthias Klein

    IPC: G06F9/46 ,  G06F13/16

    CPC classification number: G06F9/467 ,  G06F13/161

    Abstract: According to one aspect of the present disclosure, a method and technique for input/output traffic backpressure prediction is disclosed. The method includes: performing a plurality of memory transactions; determining, for each memory transaction, a traffic value corresponding to a time for performing the respective memory transactions; responsive to determining the traffic value for a respective memory transaction, determining a median value based on the determined traffic values; determining whether successive median values are incrementing; and responsive to a quantity of successively incrementing median values exceeding a threshold, indicating a prediction of a backpressure condition.

    Abstract translation: 根据本公开的一个方面，公开了一种用于输入/输出业务背压预测的方法和技术。 该方法包括：执行多个存储器事务; 为每个存储器事务确定对应于用于执行各个存储器事务的时间的业务值; 响应于确定相应存储器事务的业务值，基于所确定的业务量确定中值; 确定连续的中值是否递增; 并且响应于超过阈值的连续增加的中值的量，指示背压状态的预测。

    IMPLICIT I/O SEND ON CACHE OPERATIONS
    97.
    发明申请
    IMPLICIT I/O SEND ON CACHE OPERATIONS 有权
    隐藏I / O发送缓存操作

    公开(公告)号：US20150199273A1

    公开(公告)日：2015-07-16

    申请号：US14155495

    申请日：2014-01-15

    Applicant: International Business Machines Corporation

    Inventor： Matthias Klein ,  Marco Kraemer ,  Carsten Otte ,  Christoph Raisch

    IPC: G06F12/08

    CPC classification number: G06F12/0831 ,  G06F12/0897 ,  G06F2212/1024 ,  G06F2212/621

    Abstract: A method for implicit input-output send on cache operations of a central processing unit is provided. The method comprises an aggregation queue of a central processing unit, storing input-output data of the central processing unit, wherein the aggregation queue transmits the input-output data to an input-output adaptor, and wherein the input-output data is transmitted in parallel with operations of the central processing unit. The method further comprises, a memory management unit of the central processing unit, interpreting address space descriptors for implicit input-output transmittal of the input-output data of the aggregation queue. The method further comprises, a cache traffic monitor of the central processing unit, transmitting the input-output data in an implicit input-output transmittal range between the cache traffic monitor and the aggregation queue, wherein the cache traffic monitor transmits cache protocol of the central processing unit to the memory management unit.

    Abstract translation: 提供了一种用于中央处理单元的高速缓存操作的隐式输入输出发送方法。 该方法包括中央处理单元的聚集队列，存储中央处理单元的输入输出数据，其中聚合队列将输入输出数据传送到输入 - 输出适配器，其中输入 - 输出数据以 与中央处理单元的操作并行。 该方法还包括：中央处理单元的存储器管理单元，解释用于聚合队列的输入输出数据的隐式输入 - 输出传送的地址空间描述符。 该方法还包括：中央处理单元的高速缓存流量监视器，在高速缓存流量监视器和聚合队列之间的隐式输入 - 输出传输范围内传输输入 - 输出数据，其中高速缓存流量监视器发送中央处理器的高速缓存协议 处理单元到存储器管理单元。

    Write and read collision avoidance in single port memory devices
    98.
    发明授权
    Write and read collision avoidance in single port memory devices 有权
    在单端口存储设备中写入和读取冲突避免

    公开(公告)号：US08995210B1

    公开(公告)日：2015-03-31

    申请号：US14090060

    申请日：2013-11-26

    Applicant: International Business Machines Corporation

    Inventor： Norbert Hagspiel ,  Sascha Junghans ,  Matthias Klein ,  Joerg Walter

    IPC: G11C7/00 ,  G11C7/22 ,  G11C7/10

    CPC classification number: G11C7/1015 ,  G11C7/1075 ,  G11C2207/2209

    Abstract: A method of avoiding a write collision in single port memory devices from two or more independent write operations is described. A first write operation having a first even data object and a first odd data object is received from a first data sender. A second write operation having a second even data object and a second odd data object is received from a second data sender at substantially the same time as the first write operation. The second write operation is delayed so that the first even data object writes to a first single port memory device at a different time than the second even data object writes to the first single port memory device. The second write operation is delayed so that the first odd data object writes to a second single port memory device at a different time than the second odd data object.

    Abstract translation: 描述了避免来自两个或多个独立写入操作的单端口存储器件中的写入冲突的方法。 从第一数据发送器接收具有第一偶数数据对象和第一奇数数据对象的第一写操作。 在与第一写入操作基本相同的时间，从第二数据发送器接收具有第二偶数数据对象和第二奇数数据对象的第二写操作。 第二写操作被延迟，使得第一偶数数据对象以与第二偶数数据对象写入第一单端口存储器设备不同的时间写入第一单端口存储器设备。 第二写操作被延迟，使得第一奇数数据对象在与第二奇数数据对象不同的时间写入第二单端口存储器件。

    INPUT/OUTPUT TRAFFIC BACKPRESSURE PREDICTION
    99.
    发明申请
    INPUT/OUTPUT TRAFFIC BACKPRESSURE PREDICTION 有权
    输入/输出交通背压预测

    公开(公告)号：US20140089621A1

    公开(公告)日：2014-03-27

    申请号：US13624216

    申请日：2012-09-21

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Norbert Hagspiel ,  Matthias Klein

    IPC: G06F12/00

    CPC classification number: G06F9/467 ,  G06F13/161

    Abstract: According to one aspect of the present disclosure a system and technique for input/output traffic backpressure prediction is disclosed. The system includes a processor unit and logic executable by the processor unit to: determine, for each of a plurality of memory transactions, a traffic value corresponding to a time for performing the respective memory transactions; responsive to determining the traffic value for a respective memory transaction, determine a median value based on the determined traffic values; determine whether successive median values are incrementing; and responsive to a quantity of successively incrementing median values exceeding a threshold, indicate a prediction of a backpressure condition.

    Abstract translation: 根据本公开的一个方面，公开了一种用于输入/输出业务背压预测的系统和技术。 该系统包括处理器单元和可由处理器单元执行的逻辑，用于：对于多个存储器事务中的每一个，确定对应于用于执行各个存储器事务的时间的业务值; 响应于确定相应存储器事务的业务值，基于所确定的业务量确定中值; 确定连续中值是否递增; 并且响应于超过阈值的连续增加的中值的量，指示背压状态的预测。

    System for collaborative hardware RTL logic timing debug in integrated circuit designs
    100.
    发明授权
    System for collaborative hardware RTL logic timing debug in integrated circuit designs 有权

    公开(公告)号：US12260159B2

    公开(公告)日：2025-03-25

    申请号：US17567598

    申请日：2022-01-03

    Applicant: International Business Machines Corporation

    Inventor： Arun Joseph ,  Wolfgang Roesner ,  Shashidhar Reddy ,  Sampath Goud Baddam ,  Anthony Saporito ,  Matthias Klein

    IPC: G06F30/327 ,  G06F111/02 ,  G06F119/12

    Abstract: A method, programming product, and/or system is disclosed for identifying flaws in integrated circuits, e.g., processors, that includes: selecting from a list of a plurality of timing issues in an integrated circuit, where each timing issue on the list is represented by one or more VHDL code lines, a particular timing issue to investigate; tracing back the selected one or more VHDL code lines, corresponding to the selected particular timing issue to investigate, to one or more selected physical design VHDL (PD-VHDL) code lines; logically navigating across the one or more selected PD-VHDL code lines to one or more corresponding normalized VHDL (NVDHL) code lines; and tracing back the one or more corresponding NHVDL code lines to one or more short-hand VHDL (SVHDL) code lines to identify one or more code lines, written by a code designer, responsible for the particular timing issue being investigated.

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