公开(公告)号：US20200083090A1

公开(公告)日：2020-03-12

申请号：US16563747

申请日：2019-09-06

Applicant: IMEC VZW

Inventor： Boon Teik Chan ,  Efrain Altamirano Sanchez ,  Ryan Ryoung han Kim

IPC: H01L21/762 ,  H01L29/66 ,  H01L21/763 ,  H01L21/033 ,  H01L29/78

Abstract: A substrate includes on its surface an array of dual stack semiconductor fins, each fin comprising a monocrystalline first portion, a polycrystalline second portion, and a mask third portion. Trenches between the fins are filled with shallow trench isolation (STI) oxide and with polycrystalline material, after which the surface is planarized. Then a second mask is produced on the planarized surface, the second mask defining at least one opening, each defined opening extending across an exposed fin. A thermal oxidation is performed of the polycrystalline material on either side of the exposed fin in each defined opening, thereby producing two oxide strips in each defined opening. Using the second mask and the oxide strips as a mask for self-aligned etching, the material of the exposed dual stack fins is removed and subsequently replaced by an electrically isolating material, thereby creating gate cut structures.

公开(公告)号：US20190198643A1

公开(公告)日：2019-06-27

申请号：US16220361

申请日：2018-12-14

Applicant: IMEC vzw

Inventor： Boon Teik Chan ,  Anabela Veloso ,  Efrain Altamirano Sanchez ,  Zheng Tao

IPC: H01L29/66 ,  H01L29/08 ,  H01L29/78 ,  H01L21/3065

CPC classification number: H01L29/66666 ,  H01L21/3065 ,  H01L29/0847 ,  H01L29/42372 ,  H01L29/42392 ,  H01L29/6653 ,  H01L29/66742 ,  H01L29/7827 ,  H01L29/78642

Abstract: The disclosed technology generally relates to semiconductor devices and more particularly to a vertical channel device and a method of fabricating the same. According to one aspect, a method for fabricating a vertical channel device includes forming a vertical semiconductor structure including an upper portion, an intermediate portion and a lower portion, by etching a semiconductor layer stack arranged on a substrate. The semiconductor layer stack includes an upper semiconductor layer, an intermediate semiconductor layer and a lower semiconductor layer, wherein the intermediate semiconductor layer is formed of a material different from a material of the lower semiconductor layer and different from a material of the upper semiconductor layer. Forming the vertical semiconductor structure includes: etching the upper semiconductor layer to form the upper portion and the intermediate semiconductor layer to form the intermediate portion, detecting whether the etching has reached the lower semiconductor layer, and in response to detecting that the etching has reached the lower semiconductor layer, changing to a modified etching chemistry being different from an etching chemistry used during the etching of the intermediate semiconductor layer, and etching the lower semiconductor layer using the modified etching chemistry to form the lower portion. The modified etching chemistry is such that the lower portion is formed to present, along at least a part of the lower portion, a lateral dimension gradually increasing along a direction towards the substrate. The method further comprises forming a gate stack extending vertically along the intermediate portion to define a channel region of the vertical channel device.

公开(公告)号：US20190079384A1

公开(公告)日：2019-03-14

申请号：US16123058

申请日：2018-09-06

Applicant: IMEC VZW ,  Katholieke Universiteit Leuven, KU LEUVEN R&D

Inventor： Boon Teik Chan ,  Kim Vu Luong ,  Vicky Philipsen ,  Efrain Altamirano Sanchez ,  Kevin Vandersmissen

IPC: G03F1/24 ,  G03F1/80 ,  G03F1/58 ,  G03F7/20 ,  H01L21/768

Abstract: An example method for making a reticle includes providing an assembly. The assembly includes an extreme ultraviolet mirror and a cavity overlaying at least a bottom part of the extreme ultraviolet mirror. The method also includes at least partially filling the cavity with an extreme ultraviolet absorbing structure that includes a metallic material that includes an element selected from Ni, Co, Sb, Ag, In, and Sn, by forming the extreme ultraviolet absorbing structure selectively in the cavity.

公开(公告)号：US10090393B2

公开(公告)日：2018-10-02

申请号：US15345782

申请日：2016-11-08

Applicant: IMEC VZW

Inventor： Steven Demuynck ,  Zheng Tao ,  Boon Teik Chan ,  Liesbeth Witters ,  Marc Schaekers ,  Antony Premkumar Peter ,  Silvia Armini

IPC: H01L29/417 ,  H01L21/311 ,  H01L29/45 ,  H01L21/02 ,  H01L21/285 ,  H01L21/3105 ,  H01L21/768 ,  H01L29/08 ,  H01L29/66 ,  H01L29/78

Abstract: A method for fabricating a semiconductor structure is provided. The method includes providing a patterned substrate comprising a semiconductor region and a dielectric region. A conformal layer of a first dielectric material is deposited directly on the patterned substrate. A layer of a sacrificial material is deposited overlying the conformal layer of the first dielectric material. The sacrificial material is patterned, whereby a part of the semiconductor region remains covered by the patterned sacrificial material. A layer of a second dielectric material is deposited on the patterned substrate, thereby completely covering the patterned sacrificial material. A recess is formed in the second dielectric material by completely removing the patterned sacrificial material. The exposed conformal layer of the first dielectric material is removed selectively to the semiconductor region.

公开(公告)号：US20180182868A1

公开(公告)日：2018-06-28

申请号：US15845300

申请日：2017-12-18

Applicant: IMEC VZW

Inventor： Boon Teik Chan ,  Silvia Armini ,  Elisabeth Camerotto ,  Zheng Tao

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/06

Abstract: A method for forming horizontal nanowires, the method comprising providing a substrate comprising a dielectric layer and a fin structure comprising a portion protruding from the dielectric layer, the protruding portion being partially un-masked and comprising a multi-layer stack consisting of a layer of a first material stacked alternately and repeatedly with a layer of a second material and forming horizontal nanowires done by performing a cycle comprising removing selectively the first material up to the moment that a horizontal nanowire of the second material becomes suspended over a remaining portion of the partially un-masked protruding portion, forming a sacrificial layer on the remaining portion, while leaving the suspended horizontal nanowire uncovered, providing, selectively, a cladding layer on the suspended horizontal nanowire, and thereafter removing the sacrificial layer. The horizontal nanowires become suspended starting from the top and the cladding layer is removed, after the bottom horizontal nanowire becomes suspended.

公开(公告)号：US09899220B2

公开(公告)日：2018-02-20

申请号：US15289550

申请日：2016-10-10

Applicant: IMEC VZW ,  KATHOLIEKE UNIVERSITEIT LEUVEN, KU LEUVEN R&D

Inventor： Boon Teik Chan ,  Zheng Tao ,  Arjun Singh ,  Jan Doise

IPC: H01L21/00 ,  H01L21/033

CPC classification number: H01L21/0338 ,  G03F7/0002 ,  H01L21/0332 ,  H01L21/0335 ,  H01L21/0337 ,  H01L21/31144

Abstract: A method for patterning a substrate is disclosed. The method includes applying a first directed self-assembly (DSA) patterning process that defines a first patterned layer on top of the substrate. The pattern of the first patterned layer is to be transferred into the substrate. The method also includes applying a planarizing layer on top of the first patterned layer. The method further includes applying a second DSA patterning process that defines a second patterned layer on top of the planarizing layer, thereby not patterning the planarizing layer. A pattern of the second patterned layer is to be transferred into the substrate. Projections of the pattern of the second patterned layer and the pattern of the first patterned layer on the substrate have no overlap. Additionally, the method includes transferring the patterns defined by the first patterned layer and the second patterned layer into the substrate.

公开(公告)号：US20170170017A1

公开(公告)日：2017-06-15

申请号：US15289550

申请日：2016-10-10

Applicant: IMEC VZW ,  KATHOLIEKE UNIVERSITEIT LEUVEN, KU LEUVEN R&D

Inventor： Boon Teik Chan ,  Zheng Tao ,  Arjun Singh ,  Jan Doise

IPC: H01L21/033

CPC classification number: H01L21/0338 ,  G03F7/0002 ,  H01L21/0332 ,  H01L21/0335 ,  H01L21/0337 ,  H01L21/31144

Abstract: A method for patterning a substrate is disclosed. The method includes applying a first directed self-assembly (DSA) patterning process that defines a first patterned layer on top of the substrate. The pattern of the first patterned layer is to be transferred into the substrate. The method also includes applying a planarizing layer on top of the first patterned layer. The method further includes applying a second DSA patterning process that defines a second patterned layer on top of the planarizing layer, thereby not patterning the planarizing layer. A pattern of the second patterned layer is to be transferred into the substrate. Projections of the pattern of the second patterned layer and the pattern of the first patterned layer on the substrate have no overlap. Additionally, the method includes transferring the patterns defined by the first patterned layer and the second patterned layer into the substrate.

公开(公告)号：US20160118295A1

公开(公告)日：2016-04-28

申请号：US14919226

申请日：2015-10-21

Applicant: IMEC VZW

Inventor： Boon Teik Chan ,  Safak Sayan

IPC: H01L21/768 ,  H01L21/3105 ,  H01L21/311

CPC classification number: H01L21/76816 ,  H01L21/31051 ,  H01L21/31144 ,  H01L21/76807

Abstract: A method for forming contact vias includes providing a substrate comprising a plurality of contact structures embedded in a first dielectric layer, the contacts abutting an upper surface of the first dielectric layer. The method also includes providing a second dielectric layer on the upper surface of the first dielectric layer, and providing contact vias in the second dielectric layer by patterning the second dielectric layer at least at positions corresponding to the contact structures, wherein patterning the second dielectric layer comprises using a DSA patterning technique.

Abstract translation: 用于形成接触孔的方法包括提供包括嵌入在第一介电层中的多个接触结构的衬底，所述接触件邻接第一电介质层的上表面。 该方法还包括在第一电介质层的上表面上提供第二电介质层，并且通过至少在对应于接触结构的位置处图案化第二电介质层，在第二电介质层中提供接触通孔，其中，图案化第二电介质层 包括使用DSA图案化技术。